DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I in the reply filed on 27 February 2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 27 June 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 17-20 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventors, at the time the application was filed, had possession of the claimed invention.
Regarding claim 17, the Applicant’s specification does not support the auxiliary isolation pattern extending from the first surface, instead, the specification only describes the auxiliary isolation pattern as extending from the second surface. For this reason, claim 17 fails to comply with the written description requirement.
Claims 18-20 are rejected for their dependency on claim 17.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5, and 8-9 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Honda et al. (USPGPub 20190043901 A1).
Regarding claim 1, Honda teaches an image sensor comprising: a substrate (163) comprising a first surface and a second surface (see figure 14A, semiconductor layer 163 (i.e. substrate) having a bottom surface (i.e. first surface) and a top surface (i.e. second surface)); a plurality of pixel groups, each of the plurality of pixel groups comprising a plurality of photodiodes (65) provided in the substrate (163) (see figure 19, two pixel groups shown, each having four photodiodes 65); a pixel isolation pattern (61/62) provided between the plurality of photodiodes (65) in the substrate (163) (see figure 19, FDTI 61 and RDTI 62 separating the plurality of photodiodes 65 from one another); an auxiliary isolation pattern (81) provided in the substrate (163), the auxiliary isolation pattern (81) extending from the second surface of the substrate (163) into the substrate (163) (see figure 19, impurity layer 81 (i.e. auxiliary isolation pattern); see figure 14A, impurity layer 81 extending from the second surface into the semiconductor layer 163 (i.e. substrate); ¶167, adjacent photo diodes 65 in a right-to-left direction are separated by a P-type impurity layer 81, and adjacent photodiodes 65 in an upper-to-lower direction are separated by the P-type impurity layer 81; and NOTE: while the above paragraph is directed to a different embodiment than that shown in figure 19, it proves that the impurity layer 81 is used as an isolation element); and a micro lens (67) provided on the second surface of the substrate (163) (see figure 14A, lenses 67), wherein the pixel isolation pattern (61/62) comprises: an outer isolation pattern (61) provided between the plurality of pixel groups (see figure 19, FDTI 61 (i.e. outer isolation pattern)), and an inner isolation pattern (62) (see figure 19, RDTI 62 (i.e. inner isolation pattern)) comprising: a first inner isolation pattern provided between two first adjacent photodiodes (65), among the plurality of photodiodes (65) (see figure 19, RDTI 62 extending horizontally (i.e. first inner isolation pattern)), and a second inner isolation pattern provided between two second adjacent photodiodes (65), among the plurality of photodiodes (65) (see figure 19, RDTI 62 extending vertically (i.e. second inner isolation pattern)), and wherein the auxiliary isolation pattern (81) is provided between the outer isolation pattern (61) and one of the first and the second inner isolation patterns (62) that are spaced apart from each other or between the first inner isolation pattern and the second inner isolation pattern that are spaced apart from each other (see figure 19, impurity layer 81 (i.e. auxiliary isolation pattern) arranged between RDTIs 62 (i.e. inner isolation patterns)).
Regarding claim 2, Honda teaches the image sensor of claim 1, wherein the first inner isolation pattern and the second inner isolation pattern are spaced apart from each other at a central portion within the plurality of pixel groups (see figure 19, RDTIs 62 being separated from one another by a central portion), and the auxiliary isolation pattern (81) is provided at the central portion within the plurality of pixel groups (see figure 19, impurity layer 81 disposed in the center of the unit pixel; and ¶169, a configuration example of FIG. 19 is made such that an intersection portion between adjacent portions of the RDTI 62 in each block are separated by the P-type impurity layer 81).
Regarding claim 3, Honda teaches the image sensor of claim 2, wherein each of the plurality of pixel groups comprises four photodiodes (65) (see figure 19, each pixel group (unlabeled) having four photodiodes 65), the four photodiodes (65) are provided along a first direction and a second direction crossing the first direction (see figure 19, the four photodiodes 65 arranged in a 2x2 matrix), the first inner isolation pattern and the second inner isolation pattern extend along the first direction or the second direction (see figure 19, inner isolation patterns 62 being disposed both vertically and horizontally between adjacent photodiodes 65), and the outer isolation pattern (61) surrounds the four photodiodes (65) and is connected to the first inner isolation pattern and the second inner isolation pattern (see figure 19, FDTI 61 (i.e. outer isolation pattern) surrounding and connecting with inner isolation patterns 62).
Regarding claim 5, Honda teaches the image sensor of claim 1, wherein the auxiliary isolation pattern (81) is in contact with or spaced apart from the pixel isolation pattern (61/62) (see figure 19, impurity layer 81 (i.e. auxiliary isolation pattern) in contact with the inner isolation patterns 62).
Regarding claim 8, Honda teaches the image sensor of claim 1, wherein the pixel isolation pattern (61/62) is configured to penetrate the substrate (163) in a vertical direction (see figure 14A, isolation patterns 61, 62, and 81 penetrating the semiconductor layer 163 (i.e. substrate) vertically).
Regarding claim 9, Honda teaches the image sensor of claim 1, further comprising: a transmission transistor (72) connected to each of the plurality of photodiodes (65) (see figure 14C, transfer gates 72); and a floating diffusion area (71) connected to at least two photodiodes (65) through the transmission transistor (72) (see figure 14C, floating diffusion 71 connected to photodiodes 65 through transfer gates 72), wherein the auxiliary isolation pattern (81) overlaps the floating diffusion area (71) in a vertical direction (see figure 19, impurity layer 81 (i.e. auxiliary isolation pattern) disposed in the center of the unit pixel; see figure 14c, floating diffusion 71 disposed in the center of the unit pixel; and ¶118, A floating diffusion (FD) 71 is disposed at the center of each block, and a transfer gate (TG) 72 is disposed close to the FD 71 at each photodiode 65).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Honda et al. (USPGPub 20190043901 A1) in view of Jung et al. (USPGPub 20220109015 A1).
Regarding claim 10, Honda teaches the auxiliary isolation pattern (81) penetrating the substrate (163) (see figure 14A). However, Honda fails to explicitly teach wherein a thickness of the auxiliary isolation pattern in a vertical direction is smaller than a thickness of the substrate in the vertical direction.
However, Jung teaches a thickness of the auxiliary isolation pattern (DTI3) in a vertical direction is smaller than a thickness of the substrate (100) in the vertical direction (see figures 12 and 13, DTI3 (i.e. auxiliary isolation pattern) extending only partially through substrate 100).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Honda to incorporate the teachings of Jung to have the auxiliary isolation pattern only partially extending through the substrate because, a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions (MPEP 2144.05 II A).
Regarding claim 11, Honda as modified by Jung teaches the image sensor of claim 10, wherein the thickness of the auxiliary isolation pattern (Honda 81 | Jung DTI3) in the vertical direction is smaller than a thickness of the plurality of photodiodes (Honda 65 | Jung PCR1/PCR2) in the vertical direction (Jung, see figures 12 and 13, DTI3 (i.e. auxiliary isolation pattern) extending only partially through substrate 100 and being vertically smaller than photodiodes PCR1 and PCR1).
Claims 12 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Honda et al. (USPGPub 20190043901 A1) in view of Chung et al. (USPGPub 20220231064 A1).
Regarding claim 12, Honda teaches an image sensor comprising: a substrate (163) comprising a first surface and a second surface (see figure 14A, semiconductor layer 163 (i.e. substrate) having a bottom surface (i.e. first surface) and a top surface (i.e. second surface)); a plurality of pixel groups, each of the plurality of pixel groups comprising a plurality of photodiodes (65) provided in the substrate (163) (see figure 19, two pixels shown, each having four photodiodes 65); a pixel isolation pattern (61/62) provided between the plurality of photodiodes (65) in the substrate (163) (see figure 19, FDTI 61 and RDTI 62 separating the plurality of photodiodes 65 from one another); an auxiliary isolation pattern (81) provided in the substrate (163), the auxiliary isolation pattern (81) extending inside the substrate (163) from the second surface of the substrate (163) (see figure 19, impurity layer 81 (i.e. auxiliary isolation pattern); see figure 14A, impurity layer 81 extending from the second surface into the semiconductor layer 163 (i.e. substrate); ¶167, adjacent photo diodes 65 in a right-to-left direction are separated by a P-type impurity layer 81, and adjacent photodiodes 65 in an upper-to-lower direction are separated by the P-type impurity layer 81; and NOTE: while the above paragraph is directed to a different embodiment than that shown in figure 19, it proves that the impurity layer 81 is used as an isolation element), wherein the pixel isolation pattern (61/62) comprises: an outer isolation pattern (61) provided between the plurality of pixel groups (see figure 19, FDTI 61 (i.e. outer isolation pattern)), and an inner isolation pattern (62) (see figure 19, RDTI 62 (i.e. inner isolation pattern)) comprising: a first inner isolation pattern provided between two first adjacent photodiodes (65), among the plurality of photodiodes (65) (see figure 19, RDTI 62 extending horizontally (i.e. first inner isolation pattern)), and a second inner isolation pattern provided between two second adjacent photodiodes (65), among the plurality of photodiodes (65) (see figure 19, RDTI 62 extending vertically (i.e. second inner isolation pattern)), and wherein the auxiliary isolation pattern (81) is provided between the outer isolation pattern (61) and one of the first and the second inner isolation patterns (62) that are spaced apart from each other or between the first inner isolation pattern and the second inner isolation pattern that are spaced apart from each other (see figure 19, impurity layer 81 (i.e. auxiliary isolation pattern) arranged between RDTIs 62 (i.e. inner isolation patterns)). However, Honda fails to explicitly teach an element isolation pattern provided in the substrate, the element isolation pattern extending inside the substrate from the first surface of the substrate.
However, Chung teaches an element isolation pattern (118) provided in the substrate (106), the element isolation pattern (118) extending inside the substrate (106) from the first surface (106s1) of the substrate (106) (see figure 2A, device isolation layer 118 extending from the first surface 106s1 of the substrate 106).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Honda to incorporate the teachings of Chung to further include an element isolation layer in order to isolate the circuit components from one another, preventing unwanted interference.
Regarding claim 16, Honda as modified by Chung teaches the image sensor of claim 12, further comprising a color filter (Honda 66 | Chung 160) provided on the second surface (Chung 106s2) of the substrate (Honda 163 | Chung 106) (Honda, see figure 14A, color filter 66 disposed over the second surface of the semiconductor layer 163 (i.e. substrate)); and a micro lens (Honda 67 | Chung 170) provided on the color filter (Honda 66 | Chung 160) (Honda, see figure 14A, lenses 67 disposed on color filter 66).
Claims 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Honda et al. (USPGPub 20190043901 A1) in view of Chung et al. (USPGPub 20220231064 A1) as applied to claim 12 above, and further in view of Jung et al. (USPGPub 20220109015 A1).
Regarding claim 13, Honda as modified by Chung teaches the auxiliary isolation pattern (Honda 81) penetrating the substrate (Honda 163 | Chung 106) (Honda, see figure 14A). However, the combination fails to explicitly teach wherein a thickness of the auxiliary isolation pattern in a vertical direction is smaller than a thickness of the plurality of photodiodes in the vertical direction.
However, Jung teaches wherein a thickness of the auxiliary isolation pattern (DTI3) in a vertical direction is smaller than a thickness of the plurality of photodiodes (PCR1/PCR2) in the vertical direction (see figures 12 and 13, DTI3 (i.e. auxiliary isolation pattern) extending only partially through substrate 100 and being vertically smaller than photodiodes PCR1 and PCR1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Honda and Chung to incorporate the teachings of Jung to have the auxiliary isolation pattern only partially extending through the substrate because, a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions (MPEP 2144.05 II A).
Regarding claim 15, Honda as modified by Chung teaches the auxiliary isolation pattern (Honda 81) penetrating the substrate (Honda 163 | Chung 106) (Honda, see figure 14A). However, the combination fails to explicitly teach wherein a thickness of the auxiliary isolation pattern in a vertical direction is smaller than a thickness of the pixel isolation pattern in the vertical direction.
However, Jung teaches wherein a thickness of the auxiliary isolation pattern (DTI3) in a vertical direction is smaller than a thickness of the pixel isolation pattern (DTI1) in the vertical direction (see figures 12 and 13, DTI3 (i.e. auxiliary isolation pattern) extending only partially through substrate 100 while DTI1 extends through the entire substrate).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Honda and Chung to incorporate the teachings of Jung to have the auxiliary isolation pattern only partially extending through the substrate because, a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions (MPEP 2144.05 II A).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Honda et al. (USPGPub 20190043901 A1) in view of Chung et al. (USPGPub 20220231064 A1) and Jung et al. (USPGPub 20220109015 A1) as applied to claim 13 above, and further in view of Park et al. (USPGPub 20220123033 A1).
Regarding claim 14, Honda as modified by Chung and Jung teaches wherein a thickness of the auxiliary isolation pattern (Honda 81 | Jung DTI3) in a vertical direction is smaller than a thickness of the plurality of photodiodes (Honda 65 | Chung PD | Jung PCR1/PCR2) in the vertical direction (Jung, see figures 12 and 13, DTI3 (i.e. auxiliary isolation pattern) extending only partially through substrate 100 and being vertically smaller than photodiodes PCR1 and PCR1), However, the combination fails to explicitly teach wherein a ratio of the thickness of the auxiliary isolation pattern in the vertical direction to the thickness of the plurality of photodiodes in the vertical direction is 1:10 to 1:2.
However, Park teaches wherein a ratio of the thickness of the auxiliary isolation pattern (312) in the vertical direction to the thickness of the plurality of photodiodes (PD) in the vertical direction is 1:10 to 1:2 (see figure 11; ¶99, the pixel isolation layer 311 may have a first width W1 and a first length L1, and the intra-pixel isolation layer 312 may have a second width W2 and a second length L2; ¶100, the first length L1 may be about 1.1 µm to 1.3 µm, and the second length L2 may be about 0.2 µm to 0.4 µm; ¶101, the intra-pixel isolation layer 312 may have a length less than that of the plurality of first photodiodes PD1 in the vertical direction (Z direction); and NOTE: with the above values, it is clear that the ratio between the length of the intra-pixel isolation layer 312 and the length of the photodiode fall within this large range).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Honda, Chung, and Jung to incorporate the teachings of Park to have the ratio between the length of the isolation layer and the photodiode be within the aforementioned range because a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions (MPEP 2144.05 II A).
Claims 17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Honda et al. (USPGPub 20190043901 A1) in view of Lee et al. (USPGPub 20220149101 A1).
Regarding claim 17, Honda teaches an image sensor comprising: a substrate (163) comprising a first surface and a second surface (see figure 14A, semiconductor layer 163 (i.e. substrate) having a bottom surface (i.e. first surface) and a top surface (i.e. second surface)); a plurality of pixel groups, each of the plurality of pixel groups comprising a plurality of photodiodes (65) provided in the substrate (163) (see figure 19, two pixels shown, each having four photodiodes 65); a plurality of pixel isolation patterns (61/62), each provided between adjacent photodiodes (65) among the plurality of photodiodes (65) in the substrate (163) (see figure 19, FDTI 61 and RDTI 62 separating the plurality of photodiodes 65 from one another); and an auxiliary isolation pattern (81) provided in the substrate (163), the auxiliary isolation pattern (81) extending inside the substrate (163) from the first surface of the substrate (163) and provided between two pixel isolation patterns (61/62), among the plurality of pixel isolation patterns (61/62) spaced apart from each other (see figure 19, impurity layer 81 (i.e. auxiliary isolation pattern) arranged between RDTIs 62; see figure 14A, impurity layer 81 extending from the first surface into the semiconductor layer 163 (i.e. substrate); ¶167, adjacent photo diodes 65 in a right-to-left direction are separated by a P-type impurity layer 81, and adjacent photodiodes 65 in an upper-to-lower direction are separated by the P-type impurity layer 81; and NOTE: while the above paragraph is directed to a different embodiment than that shown in figure 19, it proves that the impurity layer 81 is used as an isolation element). However, Honda fails to explicitly teach wherein each of the plurality of pixel isolation patterns comprises: an isolation conductive pattern extending inwardly from the second surface of the substrate, a capping insulation pattern extending inwardly from the first surface of the substrate, and an isolation insulation pattern provided on side surfaces of the isolation conductive pattern and the capping insulation pattern.
However, Lee teaches wherein each of the plurality of pixel isolation patterns (13) comprises: an isolation conductive pattern (9) extending inwardly from the second surface (1b) of the substrate (1) (see figure 3, device isolation portion 13 having conductive pattern 9 extending from the second surface 1b of the substrate 1), a capping insulation pattern (11) extending inwardly from the first surface (1a) of the substrate (1) (see figure 3, filling insulation pattern 11 extending from the first surface 1a of the substrate 1), and an isolation insulation pattern (7) provided on side surfaces of the isolation conductive pattern (9) and the capping insulation pattern (11) (see figure 3, isolation insulating layer 7 surrounding conductive pattern 9 and filling insulation pattern 11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Honda to incorporate the teachings of Lee to provide a conductive isolation pattern as is can prevent the generation of dark current. Additionally, it would have been obvious to provide insulating layers with this conductive pattern in order to prevent electrical crosstalk between pixels/sensors.
Regarding claim 19, Honda as modified by Lee teaches the image sensor of claim 17, wherein the plurality of pixel isolation patterns (Honda 61/62 | Lee 13) are spaced apart from each other at a central portion within the plurality of pixel groups (Honda, see figure 19, RDTIs 62 being separated from one another by a central portion), and the auxiliary isolation pattern (Honda 81) is provided at the central portion within the plurality of pixel groups and the auxiliary isolation pattern (Honda 81) is in contact with or spaced apart from the pixel isolation pattern (Honda 61/62 | Lee 13) (Honda, see figure 19, impurity layer 81 disposed in the center of the unit pixel; and ¶169, a configuration example of FIG. 19 is made such that an intersection portion between adjacent portions of the RDTI 62 in each block are separated by the P-type impurity layer 81).
Regarding claim 20, Honda as modified by Lee teaches the image sensor of claim 17, further comprising: a transmission transistor (Honda 72 | Lee TG) connected to each of the plurality of photodiodes (Honda 65 | Lee PD) (Honda, see figure 14C, transfer gates 72); and a floating diffusion area (Honda 71 | Lee FD) connected to at least two photodiodes (Honda 65 | Lee PD) through the transmission transistor (Honda 72 | Lee TG) (Honda, see figure 14C, floating diffusion 71 connected to photodiodes 65 through transfer gates 72), wherein the auxiliary isolation pattern (Honda 81) overlaps the floating diffusion area (Honda 71) in a vertical direction (Honda, see figure 19, impurity layer 81 (i.e. auxiliary isolation pattern) disposed in the center of the unit pixel; see figure 14c, floating diffusion 71 disposed in the center of the unit pixel; and ¶118, A floating diffusion (FD) 71 is disposed at the center of each block, and a transfer gate (TG) 72 is disposed close to the FD 71 at each photodiode 65).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Honda et al. (USPGPub 20190043901 A1) in view of Lee et al. (USPGPub 20220149101 A1) as applied to claim 17 above, and further in view of Park et al. (USPGPub 20220123033 A1).
Regarding claim 18, Honda as modified by Lee teaches the auxiliary isolation pattern (Honda 81) penetrating the substrate (Honda 163 | Lee 1) (Honda, see figure 14A). However, the combination fails to explicitly teach wherein a thickness of the auxiliary isolation pattern in a vertical direction is smaller than a thickness of the plurality of photodiodes in the vertical direction.
However, Park teaches wherein a thickness of the auxiliary isolation pattern (312) in a vertical direction is smaller than a thickness of the plurality of photodiodes (PD) in the vertical direction (see figure 11; and ¶101, the intra-pixel isolation layer 312 may have a length less than that of the plurality of first photodiodes PD1 in the vertical direction (Z direction)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Honda and Lee to incorporate the teachings of Park to have the isolation pattern be shorter than the photodiode because [a]ccordingly, electric charges may move between the plurality of first photodiodes PD1 with the intra-pixel isolation layer 312 interposed therebetween. For example, when an excessive amount of electric charge is generated in any one of the plurality of first photodiodes PD1, the electric charge may move, thereby preventing saturation of the first photodiode PD1 (Park, ¶101).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Qiu et al. (USPGPub 20240153980 A1): Qiu teaches that a transfer transistor and a transmission transistor are equivalents in the art (¶8, The structure shown in FIG. 2 differs from the structure shown in FIG. 1 in terms of an additional transfer transistor, which is also referred to as a transmission transistor M4).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIN R GARBER whose telephone number is (571)272-4663. The examiner can normally be reached M-F 0730-1730.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Georgia Y Epps can be reached at (571)272-2328. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIN R GARBER/Examiner, Art Unit 2878