DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Group I and Species A, with claims 1-4, 9-11 readable thereon, in the reply filed on August 25, 2026, is acknowledged. As the election was made without traverse, the requirement is deemed proper and is therefore made FINAL.
Claim Objections
Claims 1-5, 7 are objected to because of the following informalities:
Claims 1-5, 7 include an “epi layer” which is a shortened form of the word “epitaxial.” The full-length version of the word should be included in the claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 9-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CN108550630A (“Zhang”).
RE: Claim 1, Zhang discloses A semiconductor device (device in FIG. 2), comprising:
a substrate (4);
an epi layer (3, pg. 3, lines 19-22) on an upper surface of the substrate;
a P region (combination of 2 and 10, see pg. 3, lines 24-26) located within the epi layer;
at least one N+ region (9, pg. 4, lines 8-10) located within the P region;
at least one insulating layer (left 8, right 8, pg. 4, lines 20-22) in contact with the epi layer, the P region, and the at least one N+ region; and
an anode (1, pg. 4, lines 21-22) provided on the P region, the at least one N+ region, and the at least one insulating layer.
RE: Claim 2, Zhang discloses The semiconductor device of claim 1, wherein the at least one insulating layer is one of:
located on upper surfaces of the epi layer, the P region, and the at least one N+ region (FIG. 2 shows insulating layer 8 located on upper surfaces of 3, 10, and 9); or
located in a trench structure along sides of the P region and the at least one N+ region within the epi layer.
RE: Claim 3, Zhang discloses The semiconductor device of claim 1, wherein the substrate includes at least one of an N+ type substrate (4 is a N+ semiconductor substrate, pg. 3, lines 19-20), a P+ type substrate, or any combination thereof.
RE: Claim 4, Zhang discloses The semiconductor device of claim 1, wherein the epi layer includes at least one of an N- type epi layer (3 is an N-wide bandgap epitaxial layer, pg. 3, lines 21-22), a P- type epi layer, or any combination thereof.
RE: Claim 9, Zhang discloses The semiconductor device of claim 1, wherein:
the at least one N+ region (9) includes a number of N+ regions in the range of two to four N+ regions (FIG. 2 shows two N+ regions 9); and
the at least one insulating layer (8) includes a number of insulating layers in the range of two to four insulating layers (FIG. 2 shows two insulating layers 8).
RE: Claim 10, Zhang discloses The semiconductor device of claim 1, wherein the semiconductor device further includes a cathode (5, pg. 3, lines 19-20), and wherein the cathode is located on a lower surface of the substrate (FIG. 2 shows the cathode 5 is located on a lower surface of substrate 4) or is spaced apart in a same layer as the anode.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang as applied to claim 1 above, and further in view of US11063144B2 (“Rupp”).
RE: Claim 11, Zhang does not explicitly disclose The semiconductor device of claim 1, wherein, in an on state, an inversion channel is formed in a portion where the P region and the at least one insulating layer contact each other.
However, the claimed product and the prior art product in Zhang are substantially identical in structure and therefore the device of Zhang is understood as having the same characteristics as the claimed product. Accordingly, Zhang’s device is understood as meeting the limitation wherein in an on state, an inversion channel is formed in a portion where the P region and the at least one insulating layer contact each other, see MPEP 2114 (I). Further, where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). "When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not." In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product, see MPEP 2112.01.
Further, "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. As Zhang’s device teaches all the structural limitations of the claim, the claimed device is not differentiated from Zhang’s device.
Alternatively, Zhang discloses When the voltage of the metal anode is higher than 0.1 V, the surface of the P-type wide band gap semiconductor Well region is inverted, forming an electron path from N+. The electrons of the wide bandgap semiconductor substrate passing through the N-wide bandgap semiconductor epitaxial layer and the surface inversion channel reaching the Schottky anti-bias junction interface are quickly drawn away by the anode to form a current, which is for the diode device, see pg. 11, lines 15-20.
As Zhang discloses 10 is a p-type wide band gap well region, pg. 3, lines 25-30, Zhang teaches that the surface of 10 would be inverted, and this surface of 10 would be a portion where 10 and the insulating layer 8 are in indirect contact with each other.
Alternatively, in the same field of endeavor, Rupp discloses:
The semiconductor components 500 can also be IGBTs (insulated gate bipolar transistors) or MCDs (MOS-controlled diodes), Col. 7 lines 1-3.
Rupp discloses In FIGS. 4A, 4B, 5, 6 and 7, the semiconductor component 500 is in each case a SiC MOSFET, Col. 12, lines 9-10.
Rupp discloses In the on state, the transistor cells TC, in channel regions of the body regions 125, form lateral inversion channels along the first surface 101 between the source regions 110 and the sections of the drift zone 131 that adjoin the first surface 101, Col. 13, lines 5-10.
FIG. 4A shows the portion of the first surface 101 between the n+ source regions 110 and the drift zone 131 would include a portion where a p-region 125 and gate dielectric 159 contact each other along surface 101, see Col. 12, lines 20-25.
Rupp discloses The present application relates to SiC (silicon carbide) semiconductor components, for example semiconductor switches having a low on resistance, Col. 1, lines 1-3.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang’s device to operate with an inversion channel as taught by Rupp in order to form a semiconductor device having a low on resistance.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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