Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 14/831,522, filed on September 24, 2015.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on June 27, 2024; November 11, 2024; were filed in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Status of Claims
Examiner notes that in the instant application:
-Claims 18-31 are pending.
-Claims 1-17 are cancelled.
Specification
The disclosure is objected to because of the following informalities:
The reference of continuation (to prior-filed applications) within the first sentence of the specification should be updated to include which of the prior applications are now patents.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 18-31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Moriwaki (U.S. Pub. 2013/0044284), hereinafter Moriwaki.
Regarding Claim 18, Moriwaki teaches an organic electroluminescent device ((100a) as taken as an organic electroluminescence display; Figs. 1-3 and 6-7, Paragraphs [0036] and [0107]), comprising:
-a first transistor ((30); Fig. 6, Paragraph [0053]) having a gate ((3b); Fig. 6, Paragraph [0060]), a first current terminal ((1e); Fig. 6, Paragraph [0060]), and a second current terminal ((1d); Fig. 6, Paragraph [0060]);
-a data signal line ((6a); Figs. 3 and 6, Paragraph [0054]) extending in a first direction (e.g. Y-direction in Fig. 3) and formed in a layer ((43); Fig. 6, Paragraph [0084]) over the first transistor (30);
-a first power supply line layer ((72); Fig. 6, Paragraph [0069]) extending in at least a second direction (e.g. X-direction in Fig. 3, laterally in Fig. 6), wherein the first direction (Y-direction) crosses the second direction (X-direction);
-an upper power supply line layer ((200); Fig. 6, Paragraphs [0070] and [0083]) extending in at least the first direction (Y-direction), wherein the upper power supply line layer (200) is electrically connected (via contact hole (201); Paragraph [0093]) to the first power supply line layer (72);
-a pixel electrode ((9a); Fig. 6, Paragraph [0039]) electrically connected to the first current terminal (1e) of the first transistor (30) (Paragraph [0086]);
-a capacitive element ((70); Fig. 6, Paragraph [0058]) including a first capacitive electrode ((72); Examiner notes this is equivalent to Applicants disclosure’s of a first power supply line layer (41) acting as a capacitive electrode, Instant Paragraph [00154]) and a second capacitive electrode ((73); Fig. 6, Paragraph [0069]), wherein the second capacitive electrode (73) is electrically connected (via contact hole (202); Paragraph [0093]) to the upper power supply line layer (200) and is formed in a layer ((42); Fig. 6, Paragraph [0083]) under the upper power supply line layer (200) and in a layer (42) different from the first power supply line layer (72); and
-the gate (3b) of the first transistor (30) is formed in a layer ((41); Fig. 6, Paragraph [0069]) under the first power supply line layer (72).
Regarding Claim 19, Moriwaki teaches an organic electroluminescent device ((100a) as taken as an organic electroluminescence display; Figs. 1-3 and 6-7, Paragraphs [0036] and [0107]) of Claim 18, further comprising:
-a plurality of conduction holes (e.g. (83a), (85a), (86), and (87) hereinafter (holes); Fig. 6, Paragraphs [0073] and [0092]) penetrating respective layers from a layer ((2); Fig. 6, Paragraph [0065]) on which the second current terminal (1d) of the first transistor (30) is formed to a layer ((44); Fig. 6, Paragraph [0086]) on which the pixel electrode (9a) has been formed; and
-a plurality of relay electrodes (e.g. (71), (92), (93) hereinafter (relay); Fig. 6, Paragraphs [0086]) respectively connected to the plurality of conduction holes (holes), wherein the first current terminal (1e) of the first transistor (30) is connected to the pixel electrode (9a) by the plurality of conduction holes (holes) and the plurality of relay electrodes (relay).
Regarding Claim 20, Moriwaki teaches an organic electroluminescent device ((100a) as taken as an organic electroluminescence display; Figs. 1-3 and 6-7, Paragraphs [0036] and [0107]) of Claim 18, wherein:
-the organic electroluminescent device (100a) is a top emission device (Fig. 2, Paragraph [0049]).
Regarding Claim 21, Moriwaki teaches an organic electroluminescent device ((100a) as taken as an organic electroluminescence display; Figs. 1-3 and 6-7, Paragraphs [0036] and [0107]) of Claim 18, wherein:
-the first transistor (30) is a driving transistor (as part of the driving circuit, Figs. 1-3 and 6, Paragraphs [0036] and [0046]).
Regarding Claim 22, Moriwaki teaches an organic electroluminescent device ((100a) as taken as an organic electroluminescence display; Figs. 1-3 and 6-7, Paragraphs [0036] and [0107]) of Claim 18, wherein:
-the first power supply line layer (72) overlaps at least a portion of the gate (3b) of the first transistor (30) (See Fig. 6).
Regarding Claim 23, Moriwaki teaches an organic electroluminescent device ((100a) as taken as an organic electroluminescence display; Figs. 1-3 and 6-7, Paragraphs [0036] and [0107]) of Claim 18, wherein:
-the upper power supply line layer (200) overlaps at least a portion of the gate (3b) of the first transistor (30) (See Fig. 6).
Regarding Claim 24, Moriwaki teaches an organic electroluminescent device ((100a) as taken as an organic electroluminescence display; Figs. 1-3 and 6-7, Paragraphs [0036] and [0107]) of Claim 18, wherein:
-the first power supply line layer (72) is formed in a layer ((75); Fig. 6, Paragraph [0069]) under the data signal line (6a).
Regarding Claim 25, Moriwaki teaches an organic electroluminescent device ((100a) as taken as an organic electroluminescence display; Figs. 1-3 and 6-7, Paragraphs [0036] and [0107]) of Claim 24, wherein:
-the first power supply line layer (72) is electrically connected (See below) to the second current terminal (1d) of the first transistor (30).
Regarding the limitation “electrically connected”, the Applicant provided no limiting definition in the disclosure. Claim 1 established a first transistor to which a pixel electrode is electrically connected to a first current terminal of the first transistor. The instant claim (Claim 26) now establishes that the first power supply line is electrically connected to the second current terminal of the first transistor.
Referring to the Applicant’s Specification, a pixel electrode ((E1); Fig. 4, Paragraph [00189]) is directly electrically connected (specifically such that electrons/holes may flow at all times uninterrupted) to a current terminal (right (10A); Fig. 4, Paragaph [00140]) of the right transistor (Tel) via a plurality of relay electrodes and conduction holes; and a first power supply line ((41); Fig. 4, Paragraph [00152]) is directly electrically connected to a current terminal (left (10A)) of the center-right transistor (Tdr) via a plurality of relay electrodes and conduction holes. Notably, the electrical pathing between the two current terminals is based on whether the two transistors (Tel) and (Tdr) are on.
Thus, in order for the limitations of the claims to apply to the disclosed structure (no embodiments provided wherein this is avoided) the limitation “electrically connected” could be understood as meaning “the possibility of current traveling between”.
Therefore, Moriwaki teaches that the first power supply line layer (72) is electrically connected to the electrode (71) (when the capacitor (70) is charging/discharging, current is flowing) which in turn is electrically connected via a conduction hole (83a) to the first current terminal (1e) which is electrically connected to the second terminal (1d) (When transistor (30) is on, across the channel region (1a’)). The limitation is fulfilled.
Regarding Claim 26, Moriwaki teaches an organic electroluminescent device ((100a) as taken as an organic electroluminescence display; Figs. 1-3 and 6-7, Paragraphs [0036] and [0107]) of Claim 25, wherein:
-the upper power supply line layer (200) is formed in a layer ((43); Fig. 6, Paragraph [0084]) over the first power supply line layer (72).
Regarding Claim 27, Moriwaki teaches an organic electroluminescent device ((100a) as taken as an organic electroluminescence display; Figs. 1-3 and 6-7, Paragraphs [0036] and [0107]) of Claim 24, wherein:
-the upper power supply line layer (200) is formed in a layer ((43); Fig. 6, Paragraph [0084]) over the first power supply line layer (72).
Regarding Claim 28, Moriwaki teaches an organic electroluminescent device ((100a) as taken as an organic electroluminescence display; Figs. 1-3 and 6-7, Paragraphs [0036] and [0107]) of Claim 18, wherein:
-the first power supply line layer (72) is electrically connected (See the discussion in the rejection of Claim 25 above) to the second current terminal (1d) of the first transistor (30).
Regarding Claim 29, Moriwaki teaches an organic electroluminescent device ((100a) as taken as an organic electroluminescence display; Figs. 1-3 and 6-7, Paragraphs [0036] and [0107]) of Claim 28, wherein:
-the upper power supply line layer (200) is formed in a layer ((43); Fig. 6, Paragraph [0084]) over the first power supply line layer (72).
Regarding Claim 30, Moriwaki teaches an organic electroluminescent device ((100a) as taken as an organic electroluminescence display; Figs. 1-3 and 6-7, Paragraphs [0036] and [0107]) of Claim 18, wherein:
-the upper power supply line layer (200) is formed in a layer ((43); Fig. 6, Paragraph [0084]) over the first power supply line layer (72).
Regarding Claim 31, Moriwaki teaches an organic electroluminescent device ((100a) as taken as an organic electroluminescence display; Figs. 1-3 and 6-7, Paragraphs [0036] and [0107]) of Claim 18, wherein:
-the data signal line (6a) overlaps the first transistor (30). (See Fig. 6)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRI MIHALIOV whose telephone number is (571)270-5220. The examiner can normally be reached weekdays 7:30 - 17:30 US Eastern Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DMITRI MIHALIOV/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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