DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 15-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 15 and 17 recite the limitation "the second source/drain region" in page 4. There is insufficient antecedent basis for this limitation in the claim.
Claims 16 and 18-20 are rejected under 35 U.S.C. 112(b) since they depend upon and require all the limitations of claim 15.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 7-14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Su et al. (US 20220130823 A1; hereinafter Su).
Regarding claim 1, FIGS. 2A-9B of Su teach a transistor device (200 ¶ [0013], [0015], [0032]), comprising: a stack of semiconductor channels (208 ¶ [0016]); a first source/drain region (212D) on a first end of the semiconductor channels (first end of 208 ¶ [0016]); a second source/drain region (212S) on a second end of the semiconductor channels (second end of 208 ¶ [0016]), wherein the first source/drain region (212D) and the second source/drain region (212S) have a top surface (top surface of 212D/212S facing 217) and a bottom surface (bottom surface of 212D/212S facing 244); a first source/drain contact (218) electrically coupled to the top surface of the first source/drain region (top surface of 212D ¶ [0021]); and a second source/drain contact (242, 244) electrically coupled to the bottom surface of the second source/drain region (bottom surface of 212S ¶ [0027],[0031]), wherein a top surface of the second source/drain contact (top surface of 242, 244) is separated from the second source/drain region (212S) by an interfacial layer (238 ¶ [0026]), the interfacial layer (238) comprising a single material layer (238) continuous along the top surface and side surfaces of the second source/drain contact (top and side surfaces of 242, see FIG. 9A), and wherein the second source/drain contact (242, 244) has a bottommost surface (bottommost surface of 244) below a bottommost surface of the interfacial layer (bottommost surface of 238).
Regarding claim 2, Su teaches the transistor device of claim 1, and FIG. 9A wherein the second source/drain contact (242, 244) extends into the second source/drain region (212S).
Regarding claim 7, Su teaches the transistor device of claim 1, and FIG. 9A of Su further teaches further comprising: an isolation layer (204 ¶ [0016]) over the bottom surface of the second source/drain region (bottom surface of 212S), wherein the second source/drain contact (242, 244) passes through the isolation layer (204).
Regarding claim 8, Su teaches the transistor device of claim 7, and FIG. 9A of Su further teaches wherein the interfacial layer (238) separates the second source/drain contact (242, 244) from the isolation layer (204) through an entire thickness of the isolation layer (204).
Regarding claim 9, Su teaches the transistor device of claim 7, and FIG. 9A of Su further teaches wherein the interfacial layer (238) separates the second source/drain contact (242, 244) from the isolation layer (204) through a portion of a thickness of the isolation layer (204).
Regarding claim 10, Su teaches the transistor device of claim 1, and FIGS. 5A and 9A of Su further teach wherein the bottom surface of the second source/drain region (bottom surface of 212S) comprises a trench (236 ¶ [0025]).
Regarding claim 11, Su teaches the transistor device of claim 10, and FIG. 9A of Su further teaches wherein the interfacial layer (238) lines the trench (236), and wherein the second source/drain contact (242, 244) fills the trench (236).
Regarding claim 12, Su teaches the transistor device of claim 1, and FIG. 9A of Su further teaches wherein the second source/drain contact (242, 244) comprise a stack of different conductive materials (materials of 242 and 244 ¶ [0027],[0031]).
Regarding claim 13, Su teaches the transistor device of claim 1, and FIG. 9A of Su further teaches wherein the stack of semiconductor channels (208) comprises a stack of nanowire or nanoribbon channels (208 ¶ [0016]).
Regarding claim 14, Su teaches the transistor device of claim 1, and FIG. 9A of Su further teaches wherein the second source/drain contact (242, 244) comprises a first width (first width of 244) and a second width that is smaller than the first width (second width of 242).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Su.
Regarding claim 6, Su teaches the transistor device of claim 1.
Su does not explicitly teach wherein a thickness of the interfacial layer is less than 15 nm. However, Su teaches wherein a thickness of an interfacial layer (239 ¶ [0043]) is less than 15 nm (¶ [0044]). Additionally, Su teaches wherein a thickness of a silicide layer (240 ¶ [0026]) is between 1 nm and 10 nm (¶ [0027]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the interfacial layer taught by Su with the thickness of the other embodiment of the interfacial layer/silicide layer taught by Su since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the thickness of the interfacial layer determines the resulting device dimensions making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Su in view of Glass et al. (US 20130285155 A1; hereinafter Glass).
Regarding claim 15, FIGS. 9A-9B of Su teaches a nanowire or nanoribbon transistor (200 ¶ [0013],[0015],[0032]), comprising: a stack of semiconductor channels (208 ¶ [0016]); a gate stack (210) over the semiconductor channels (208 ¶ [0016]); source/drain regions (regions 212D, 212S shown in FIG. 9A) on opposite ends of the semiconductor channels (208 ¶ [0016]); a first contact (an instance of 218) to a first surface of the source/drain regions (first surface of 212D, 212S ¶ [0021]); and a second contact (242, 244) to a second surface of the source/drain regions (second surface of 212S), wherein a top surface of the second source/drain contact (top surface of 242, 244) is separated from the second source/drain region (212S) by an interfacial layer (238 ¶ [0026]), the interfacial layer (238) comprising a single material layer (238) continuous along the top surface and side surfaces of the second source/drain contact (e.g. top surface and side surfaces of 242, see FIG. 9A), and wherein the second source/drain contact (242, 244) has a bottommost surface (e.g. bottommost surface of 244) below a bottommost surface of the interfacial layer (bottommost surface of 238, see FIG. 9A).
Su does not teach an electronic system, comprising: a board; an electronic package attached to the board; and a die electrically coupled to the electronic package, wherein the die comprises: the nanowire or nanoribbon transistor.
FIG. 8 of Glass teaches an electronic system (1000), comprising: a board (1002); an electronic package (1004) attached to the board (1002); and a die (die package ¶ [0058]) electrically coupled to the electronic package (1004), wherein the die (die package) comprises a nanowire or nanoribbon transistor (¶ [0056]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the transistor device taught by Su with the electronic device taught by Glass for the purpose of enhancing the functionality of the electronic device taught by Glass by reducing gate-drain capacitance and improving performance (¶ [0014]) since it has been held in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007), MPEP 2143(I)(A), that examples of rationales that may support a conclusion of obviousness include combining prior art elements according to known methods to yield predictable results, wherein in the instant case MBC transistors including backside power rails are taught in the art, one having ordinary skill in the art could have combined MBC transistors including backside power rails with the electronic device taught by Glass with each element performing the same function as it does separately, and one having ordinary skill in the art would have found the combination predictable since the components are commonly used together.
Regarding claim 16, Su as modified teaches the electronic system of claim 15, and FIGS. 5A and 9A of Su further teaches further comprising: an isolation layer (204) over the second surface of the source/drain regions (second surface of 212S ¶ [0016]), wherein a hole (236 ¶ [0025]) is disposed through the isolation layer (204), and wherein the interfacial layer (238) lines the hole (236).
Regarding claim 17, Su as modified teaches the electronic system of claim 15, and FIG. 9A of Su further teaches wherein the second source/drain contact (242) extends into the second source/drain region (region 212S).
Regarding claim 18, Su as modified teaches the electronic system of claim 15, and FIG. 5 of Glass further teaches further comprising a memory chip (DRAM) coupled to the board (1002 ¶ [0044]).
Regarding claim 19, Su as modified teaches the electronic system of claim 15, and FIG. 5 of Glass further teaches further comprising a communications chip (1006) coupled to the board (1002 ¶ [0044]).
Regarding claim 20, Su as modified teaches the electronic system of claim 15, and FIG. 5 of Glass further teaches further comprising a battery (Battery) coupled to the board (1002 ¶ [0044]).
Allowable Subject Matter
Claims 3-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 3 recites the transistor device of claim 1, wherein the interfacial layer is a semiconductor material.
Su teaches the transistor device of claim 1.
However, the prior art fails to teach or reasonably suggest “wherein the interfacial layer is a semiconductor material” together with all the limitations of claims 1 and 3 as claimed. Claims 4-5 contain allowable subject matter insofar as they depend upon and require all the limitations of claims 1 and 3.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nora T Nix whose telephone number is (571)270-1972. The examiner can normally be reached Monday - Friday 9:00 am - 5:00 pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nora T. Nix/Assistant Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
Prosecution Insights