Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8 – 9, 16 – 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 8, recites: “ … wherein the interconnect is configurable to is configurable to transmit input data … ” in which “ is configurable to ” is repeated. Please clarify it. For examination purpose, examiner is assuming this section in claim 8 is “ … wherein the interconnect is configurable to transmit input data … ”.
Regarding Claim 9, recites: “ … the first circuitry … the second circuitry … ” in which “ first circuitry ” and “ second circuitry ” are both absent in claim 1. Please clarify it.
Regarding Claim 16, First, claim 16 cited “ … first circuitry to perform a first function and second circuitry to concurrently perform a second function … ” could not be found or supported in the original specification, please clarify it. Second, claim 16 cited “ a host interface configurable to receive a data packet from a network ” conflicts with FIG. 2, please clarify it. For examination purpose, examiner is assuming this section in claim 16 is “ a network interface configurable to receive a data packet from a network ”. Third, claim 16 cited “ a third function based on the first function or the second function ” could not be found or supported in the original specification, please clarify it. Fourth, claim 16 cited “ an interconnect configurable to transmit the data packet to an accelerator block of the plurality of accelerator blocks die to perform one or more operations ” in which “ accelerator blocks die ” should be “ accelerator blocks ”, please clarify it.
Regarding Claim 17 – 20, recited “ The integrated circuit die of claim 16 … ”, but claim 16 is “ A system ”, please clarify it.
Regarding Claim 19, recited “ receive the data packet from the host interface ” and “ a threshold flow rate ” could not be found or supported in the original specification, please clarify them.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 8, 10 – 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Loh ( Pub. No. US 20140181458 A1 ), hereinafter Loh.
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Regarding Independent Claim 1, Loh teaches a multi-die package, comprising:
a first die ( Loh, FIG.1, logic die 122 having 132; [0027], in some embodiments one or more logic die 122 implement a reconfigurable logic device 132 to perform data manipulation operations and other memory-related operations in accordance with a programmed logic configuration ); and
a second die ( Loh, FIG. 1, logic die 122 having 140; [0029], Moreover, in some embodiments one or more logic die 122 implement a data translation controller 140 to perform data translation operations for data received at, stored in, or accessed from, the set of one or more stacked memory die 120 ) comprising storage compression and decompression ( Loh, The data translation controller 140 is coupled to the memory controller 130 and comprises logic and other circuitry to support one or more data translation operations, which may include encryption or decryption operations, compression or decompression operations, data format translations, data element ordering, data swizzling or other bit-shifting for wear leveling, and the like ) hardware acceleration circuitry accessible ( Lio, FIG. 1, 150; [0032], In the depicted implementation of FIG. 1, the die-stacked memory device 102 is implemented in a vertical stacking arrangement whereby power and signaling are transmitted between the logic dies 122 and the memory dies 120 using dense through silicon vias (TSVs) 150 or other vertical interconnects ) by the first die ( Loh, FIG.1, logic die 122 having 132 ).
Regarding Claim 2, Loh teaches the multi-die package as claimed in claim 1, on which this claim is dependent, Loh further teaches:
wherein the first die ( Loh, FIG.1, logic die 122 having 132 ) is stacked on top of the second die ( Loh, FIG. 1, logic die 122 having 140 ).
Regarding Claim 3, Loh teaches the multi-die package as claimed in claim 2, on which this claim is dependent, Loh further teaches:
comprising external memory ( Loh, FIG. 1, 120; [0025], memory dies 120 ) communicatively coupled to ( Loh, [0030], In some embodiments, the memory controller 130 acts as the interface between the eternal devices 104-107 and the on-die logic (e.g., the reconfigurable logic device 132 or the data translation controller 140). ) the first die ( Loh, [0027], In addition to implementing logic to facilitate access to the memory implemented by the memory die 120, in some embodiments one or more logic die 122 implement a reconfigurable logic device 132 to perform data manipulation operations and other memory-related operations in accordance with a programmed logic configuration ) and the second die ( Loh, [0029], Moreover, in some embodiments one or more logic die 122 implement a data translation controller 140 to perform data translation operations for data received at, stored in, or accessed from, the set of one or more stacked memory die 120 ), wherein the external memory ( Loh, FIG. 1, 120 ) is stacked on top of the second die ( Loh, FIG. 1, logic die 122 having 140 ).
Regarding Claim 4, Loh teaches the multi-die package as claimed in claim 1, on which this claim is dependent, Loh further teaches:
wherein the second die ( Loh, FIG. 1, logic die 122 having 140 ) comprises additional circuitry comprising transportation encryption/decryption ( Loh, [0049], For example, the data translation logic 510 may support both endian format translation and encryption/decryption operations ) circuitry, network flow search hardware acceleration circuitry, flow rate control hardware acceleration circuitry, or distributed denial of service hardware acceleration circuitry.
Regarding Claim 5, Loh teaches the multi-die package as claimed in claim 1, on which this claim is dependent, Loh further teaches:
wherein the second die ( Loh, FIG. 1, logic die 122 having 140 ) comprises a network ( Loh, [0021], a network router; [0023], network interface controllers (NICs) ) of memory circuits ( Loh, [0060], network interface, may implement a direct memory access (DMA) transfer to write data from a disk or network interface directly to the die-stacked memory device 102 ) comprising lookup tables ( Loh, [0050], In some embodiments, the data translation operations performed by the data translation logic 510 may require or benefit from access to certain translation metadata, such as encryption keys, user identifiers, look-up tables ) and intermediate packet buffers ( Loh, [0026], The memory controller 130 supports the utilization of the memory cell circuitry 126 as system memory or other memory shared within the processing system 100, and thus includes circuitry to facilitate the reception, buffering, and servicing of memory access requests. This circuitry can include, for example, receivers and line drivers, memory request buffers, scheduling logic, row/column decode logic, refresh logic, data-in and data-out buffers ).
Regarding Claim 6, Loh teaches the multi-die package as claimed in claim 1, on which this claim is dependent, Loh further teaches:
wherein the first die comprises an interconnect ( Lio, FIG. 1, 150; [0032], In the depicted implementation of FIG. 1, the die-stacked memory device 102 is implemented in a vertical stacking arrangement whereby power and signaling are transmitted between the logic dies 122 and the memory dies 120 using dense through silicon vias (TSVs) 150 or other vertical interconnects ) configurable to communicatively couple the first die ( Loh, FIG.1, logic die 122 having 132 ) and the second die ( Loh, FIG. 1, logic die 122 having 140 ).
Regarding Claim 7, Loh teaches the multi-die package as claimed in claim 6, on which this claim is dependent, Loh further teaches:
wherein the interconnect ( Lio, FIG. 1, 150 ) is configurable to selectively ( Loh, [0018], a configuration controller can program a reconfigurable logic fabric of the reconfigurable logic device using a selected one of the configuration files. The particular configuration file used to program the reconfigurable logic fabric can be selected based on a software-accessible configuration element; [0028], the reconfigurable logic device 132 can implement a configuration controller 136 at one or more logic die 122 so as to provide in-system programmability for the reconfigurable logic fabric 134. The configuration controller 136 has access to a configuration store that stores one or more configuration files that may be used to program the reconfigurable logic fabric 134 ) pass data to one or more primitive circuits of the second die ( Loh, FIG. 1, logic die 122 having 140 ).
Regarding Claim 8, Loh teaches the multi-die package as claimed in claim 7, on which this claim is dependent, Loh further teaches:
wherein the interconnect ( Lio, FIG. 1, 150 ) is configurable ( Loh, FIG. 1, 132; [0030], Moreover, in some embodiments, the memory controller 130 acts as the interface between the on-die logic (e.g., the reconfigurable logic device 132 or the data translation controller 140) and the memory dies 120 … To illustrate, the reconfigurable logic device 132 can implement a specially-tailored memory interface that implements a memory scheduling algorithm specific to pre-specified or learned memory access patterns. ) to transmit input data from the first die ( Loh, FIG.1, logic die 122 having 132 ) to the second die ( Loh, FIG. 1, logic die 122 having 140 ) and transmit processed data from the second die ( Loh, FIG. 1, logic die 122 having 140 ) to the first die ( Loh, FIG.1, logic die 122 having 132 ) ( Loh, [0032], signaling are transmitted between the logic dies 122 and the memory dies 120 using dense through silicon vias (TSVs) 150 or other vertical interconnects; [0058], The processing of data at the die-stacked memory device 102 can include any of the receive-translate-store operations, access-translate-output operations, access-translate-store operations, or receive-translate-store-access-translate-output operations described above, as well as various combinations thereof or modifications thereto ).
Regarding Independent Claim 10, Loh teaches a multi-die package, comprising:
a first die ( Loh, FIG.1, logic die 122 having 132; [0027], in some embodiments one or more logic die 122 implement a reconfigurable logic device 132 to perform data manipulation operations and other memory-related operations in accordance with a programmed logic configuration ) configurable to:
receive a data packet ( Loh, FIG. 3, 303, 305 ) from a network ( FIG. 1, [0021], [0023], [0060], [0067], [0069], [0075] ); and
transmit the data packet based on a packet header ( Loh, [0070] ) of the data packet; and
a second die ( Loh, FIG. 1, logic die 122 having 140; [0029], Moreover, in some embodiments one or more logic die 122 implement a data translation controller 140 to perform data translation operations for data received at, stored in, or accessed from, the set of one or more stacked memory die 120 ) comprising a plurality of accelerator blocks ( Loh, FIG. 1, FIG. 5, FIG. 10, 140; [0029], The data translation controller 140 is coupled to the memory controller 130 and comprises logic and other circuitry to support one or more data translation operations, which may include encryption or decryption operations, compression or decompression operations ), wherein the second die ( Loh, FIG. 1, logic die 122 having 140 ) is configured to:
receive ( Lio, FIG. 1, 150; [0032], In the depicted implementation of FIG. 1, the die-stacked memory device 102 is implemented in a vertical stacking arrangement whereby power and signaling are transmitted between the logic dies 122 and the memory dies 120 using dense through silicon vias (TSVs) 150 or other vertical interconnects ) the data packet ( Loh, FIG. 5, 503, 505 ) from the first die ( Loh, FIG.1, logic die 122 having 132 ); and
perform an operation ( Loh, [0049], the data translation controller 140 implements data translation logic 510 that is configured to perform one or more data translation operations on input data to generate translated output data ) on the data packet via at least one accelerator blocks ( Loh, FIG. 1, FIG. 5, FIG. 10, 140; [0029], compression or decompression operations ) of the plurality of accelerator block.
Regarding Claim 11, Loh teaches the multi-die package as claimed in claim 10, on which this claim is dependent, Loh further teaches:
wherein an accelerator block ( Loh, FIG. 1, FIG. 5, FIG. 10, 140; [0029], compression or decompression operations ) of the plurality of accelerator blocks comprises a storage compression and decompression hardware accelerator.
Regarding Claim 12, Loh teaches the multi-die package as claimed in claim 10, on which this claim is dependent, Loh further teaches:
wherein the plurality of accelerator blocks ( Loh, FIG. 1, FIG. 5, FIG. 10, 140; [0029], compression or decompression operations ) comprises a network flow search hardware accelerator configurable to determine a destination ( Loh, [0050] In some embodiments, the data translation operations performed by the data translation logic 510 may require or benefit from access to certain translation metadata, such as encryption keys, user identifiers, look-up tables, address translation tables, and the like; [0070], a target address where the sorted data block is to be stored ) of the data packet.
Regarding Claim 13, Loh teaches the multi-die package as claimed in claim 10, on which this claim is dependent, Loh further teaches:
wherein the plurality of accelerator blocks ( Loh, FIG. 1, FIG. 5, FIG. 10, 140; [0029], compression or decompression operations ) comprises a storage compression/decompression hardware accelerator configurable ( Loh, [0049] To this end, the data translation controller 140 implements data translation logic 510 that is configured to perform one or more data translation operations on input data to generate translated output data. In some embodiments, the data translation logic 510 may be implemented at least in part as reconfigurable logic 512, such as the reconfigurable logic fabric 134 described above ) to compress and decompress the data packet.
Regarding Claim 14, Loh teaches the multi-die package as claimed in claim 10, on which this claim is dependent, Loh further teaches:
wherein the first die ( Loh, FIG.1, logic die 122 having 132 ) comprises an interconnect ( Lio, FIG. 1, 150; [0032], In the depicted implementation of FIG. 1, the die-stacked memory device 102 is implemented in a vertical stacking arrangement whereby power and signaling are transmitted between the logic dies 122 and the memory dies 120 using dense through silicon vias (TSVs) 150 or other vertical interconnects ) configurable ( Loh, [0028], the reconfigurable logic device 132 can implement a configuration controller 136 at one or more logic die 122 so as to provide in-system programmability for the reconfigurable logic fabric 134 ) to access each accelerator block ( Loh, FIG. 1, FIG. 5, FIG. 10, 140; [0029], compression or decompression operations ) of the plurality of accelerator blocks and transmit the data packet to an accelerator block of the plurality of accelerator blocks.
Regarding Claim 15, Loh teaches the multi-die package as claimed in claim 10, on which this claim is dependent, Loh further teaches:
wherein the first die ( Loh, FIG.1, logic die 122 having 132 ) comprises:
a host interface configurable to couple to a host processor (); and
a memory interface ( Lio, FIG. 1, 150; [0032], In the depicted implementation of FIG. 1, the die-stacked memory device 102 is implemented in a vertical stacking arrangement whereby power and signaling are transmitted between the logic dies 122 and the memory dies 120 using dense through silicon vias (TSVs) 150 or other vertical interconnects; FIG. 3, 303; [0036], memory access request 303 ) configurable to couple to one or more memory devices ( Loh, FIG. 1, 120; [0025], memory dies 120 ).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9, 16 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Loh, in view of Kwan ( Pub. No. US 20060092837 A1 ), herein after Kwan.
Regarding Claim 9, Loh teaches the multi-die package as claimed in claim 1, on which this claim is dependent,
Loh does not explicitly teach:
wherein the first circuitry is configurable to handle incoming data packets and adjusting a rate of the incoming data packets and the second circuitry is configurable to receive remote flow control messages and stalling transmission of the data packets in response to receiving the remote flow control messages.
However, Kwan teaches:
wherein the first circuitry ( Kwan, [0028], The dynamic threshold scheme may allow that ingress buffer resources of the flow control sender 20 be partitioned into three types of buffer pools including headroom, reserve, and shared; [0037], A controller 30 is provided to monitor the congestion at each ingress port and CG ) is configurable to handle incoming data packets and adjusting a rate of the incoming data packets and the second circuitry ( Kwan, [0046], Thus, if the ingress port utilization counter SH-IP reaches the DTCG0, the controller 30 would send an XOFF message to the flow control receiver 22 identifying an XOFF state as a current state of the ingress port for CG0; [0053], When the flow control receiver 22 receives the XOFF message from the ingress port in the flow control sender for a particular CG, the XOFF message affects the flow control receiver egress port's scheduler 24 such that all COS queues within the specified CG are no longer scheduled for service until the XON message is received ) is configurable to receive remote flow control messages and stalling transmission of the data packets in response to receiving the remote flow control messages.
Loh and Kwan are both considered to be analogous to the claimed invention because they are forming the flow control in transmission of data over a digital communication network. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Loh ( stacked first die and second die ), to incorporate the teachings of Kwan ( flow control sender 20, A controller 30, flow control receiver 22, the flow control receiver egress port's scheduler 24 ), to implement the first circuitry and the second circuitry. Doing so would provide specific circuitries, and therefore to prevent package loss and buffer overflow during congestion, and preserve transmission of higher priority, for the flow control in transmission of data over a digital communication network.
Regarding Independent Claim 16, Loh teaches a system, comprising
a first die ( Loh, FIG.1, logic die 122 having 132; [0027], in some embodiments one or more logic die 122 implement a reconfigurable logic device 132 to perform data manipulation operations and other memory-related operations in accordance with a programmed logic configuration ) comprising:
a host ( ps. this should be network ) interface ( Loh, [0021], a network router; [0023], network interface controllers (NICs) ) configurable to receive a data packet from a network ( Loh, [0060], network interface, may implement a direct memory access (DMA) transfer to write data from a disk or network interface directly to the die-stacked memory device 102 );
a second integrated circuit die ( Loh, FIG. 1, logic die 122 having 140; [0029], Moreover, in some embodiments one or more logic die 122 implement a data translation controller 140 to perform data translation operations for data received at, stored in, or accessed from, the set of one or more stacked memory die 120 ) comprising a plurality of accelerator blocks ( Loh, FIG. 1, FIG. 5, FIG. 10, 140; [0029], The data translation controller 140 is coupled to the memory controller 130 and comprises logic and other circuitry to support one or more data translation operations, which may include encryption or decryption operations, compression or decompression operations ) accessible ( Lio, FIG. 1, 150; [0032], In the depicted implementation of FIG. 1, the die-stacked memory device 102 is implemented in a vertical stacking arrangement whereby power and signaling are transmitted between the logic dies 122 and the memory dies 120 using dense through silicon vias (TSVs) 150 or other vertical interconnects ) by the first die ( Loh, FIG.1, logic die 122 having 132 ) and configured to perform a third function ( Loh, [0029], compression or decompression operations ); and
an interconnect ( Lio, FIG. 1, 150 ) configurable to transmit the data packet to an accelerator block ( Loh, FIG. 1, FIG. 5, FIG. 10, 140 ) of the plurality of accelerator blocks die to perform one or more operations.
Loh does not explicitly teach:
programmable logic comprising first circuitry to perform a first function and second circuitry to concurrently perform a second function; and
However, Kwan teaches:
programmable logic comprising first circuitry ( Kwan, [0028], The dynamic threshold scheme may allow that ingress buffer resources of the flow control sender 20 be partitioned into three types of buffer pools including headroom, reserve, and shared; [0037], A controller 30 is provided to monitor the congestion at each ingress port and CG ) to perform a first function and second circuitry ( Kwan, [0046], Thus, if the ingress port utilization counter SH-IP reaches the DTCG0, the controller 30 would send an XOFF message to the flow control receiver 22 identifying an XOFF state as a current state of the ingress port for CG0; [0053], When the flow control receiver 22 receives the XOFF message from the ingress port in the flow control sender for a particular CG, the XOFF message affects the flow control receiver egress port's scheduler 24 such that all COS queues within the specified CG are no longer scheduled for service until the XON message is received ) to concurrently perform a second function; and
Loh and Kwan are both considered to be analogous to the claimed invention because they are forming the flow control in transmission of data over a digital communication network. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Loh ( stacked first die and second die ), to incorporate the teachings of Kwan ( flow control sender 20, A controller 30, flow control receiver 22, the flow control receiver egress port's scheduler 24 ), to implement the first circuitry and the second circuitry. Doing so would provide specific circuitries, and therefore to prevent package loss and buffer overflow during congestion, and preserve transmission of higher priority, for the flow control in transmission of data over a digital communication network.
Regarding Claim 17, Loh and Kwan teach the integrated circuit die ( ps. this should be “ the system ” ) as claimed in claim 16, on which this claim is dependent, Loh further teaches:
comprising a packet processing pipeline configurable to parse ( Loh, [0070], allow the data translation controller 140 to parse the individual data elements out of (the data block ) packets, validate ( Loh, [0064], in response to a valid user authentication ) packets, extract a flow key ( Loh, [0050], encryption keys ) from the data packet, or perform an operation.
Regarding Claim 18, Loh and Kwan teach the integrated circuit die ( ps. this should be “ the system ” ) as claimed in claim 16, on which this claim is dependent, Loh further teaches:
wherein the interconnect ( Lio, FIG. 1, 150 ) is configurable to couple the programmable logic ( Loh, FIG.1, logic die 122 having 132; [0027], in some embodiments one or more logic die 122 implement a reconfigurable logic device 132 ) to each accelerator block ( Loh, FIG. 1, FIG. 5, FIG. 10, 140 ) of the plurality of accelerator blocks.
Regarding Claim 19, Loh and Kwan teach the integrated circuit die ( ps. this should be “ the system ” ) as claimed in claim 16, on which this claim is dependent, Kwan further teaches:
wherein the first circuitry ( Kwan, [0028], The dynamic threshold scheme may allow that ingress buffer resources of the flow control sender 20 be partitioned into three types of buffer pools including headroom, reserve, and shared; [0037], A controller 30 is provided to monitor the congestion at each ingress port and CG ) is configurable to:
receive the data packet from the host interface;
generate a flow rate control ( Kwan, [0028], flow control sender 20 ) message relating to transmission based on a flow rate of the data packet being greater than a threshold flow rate ( Kwan, Abstract, comparing the dynamic threshold of each CG with the ingress port utilization counter, and determining a particular CG experiencing congestion when the ingress port utilization counter is greater than the dynamic threshold for the particular CG ); and
determine a priority ( Loh, [0018], Best effort traffic (i.e., low priority traffic) may be separately flow controlled at the discretion of user settings, thereby maintaining the high priority traffic on the link as long as possible ) to transmit the data packet based on one or more additional data packets queued for transmission.
Regarding Claim 20, Loh and Kwan teach the integrated circuit die ( ps. this should be “ the system ” ) as claimed in claim 16, on which this claim is dependent, Kwan further teaches:
wherein the second circuitry ( Kwan, [0046], Thus, if the ingress port utilization counter SH-IP reaches the DTCG0, the controller 30 would send an XOFF message to the flow control receiver 22 identifying an XOFF state as a current state of the ingress port for CG0; [0053], When the flow control receiver 22 receives the XOFF message from the ingress port in the flow control sender for a particular CG, the XOFF message affects the flow control receiver egress port's scheduler 24 such that all COS queues within the specified CG are no longer scheduled for service until the XON message is received ) is configurable to:
receive a remote flow control message ( Kwan, [0046], XOFF message, XON message ); and
stall ( Kwan, [0046], the XOFF message affects the flow control receiver egress port's scheduler 24 such that all COS queues within the specified CG are no longer scheduled for service until the XON message is received ) transmission of the data packets in response to receiving the remote flow control message ( Kwan, [0046], XOFF message, XON message ).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
Prosecution Insights