DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to amendment filed on 12/23/2025.
The specification has been amended.
No claims have been amended.
The objections and rejections from the prior correspondence that are not restated herein are withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2, 11-14, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nagarakatte et al. (US 2023/0376733), Narayanaswami et al. (US 2018/0197068), and Deisher et al. (US 2018/0121796).
With respect to claim 1, Nagarakatte teaches of a memory circuit, comprising: a first buffer configured to store a plurality of first data elements (fig. 4; paragraph 32, 34; SRAM 484 stores the filters/weights);
a second buffer configured to store a plurality of second data elements (fig. 4; paragraph 34; SRAM 482 stores the input feature map (ifmap));
an array comprising a plurality of processing elements (PEs), each of the PEs including a plurality of storage cells (fig. 4; paragraph 36, 81; where the GEMM is made up of an array of processing elements. Each PE includes three FIFO buffers as well as multiple registers); and
a data router configured to determine whether to store, in the storage cells of each of the PEs, a corresponding one of the plurality of first data elements or corresponding ones of the plurality of second data elements (fig. 4-5; paragraph 37, 45, 81; the GEMM input controller controls the input of the filters/weights and the input feature map (ifmap) to the PEs of the GEMM. The inputs are received in the PE in the appropriate FIFO buffer of each PE).
Nagarakatte fails to explicitly teach of (1) a controller configured to generate a control signal based on a layer type; (2) a data router configured to receive the control signal and determine whether to store, in the storage cells of each of the PEs, a corresponding one of the plurality of first data elements or corresponding ones of the plurality of second data elements based on the control signal.
However, Narayanaswami teaches of a memory circuit, comprising: a first buffer configured to store a plurality of first data elements (fig. 1; paragraph 29; second bank for storing weights);
a second buffer configured to store a plurality of second data elements (fig. 1; paragraph 29; first bank for storing activations);
a controller configured to generate a control signal based on a layer type (fig. 1, 3; paragraph 44, 46; where the instruction specifies the type of layer);
Narayanaswami fails to explicitly teach of a data router configured to receive the control signal and determine whether to store, in the storage cells of each of the PEs, a corresponding one of the plurality of first data elements or corresponding ones of the plurality of second data elements based on the control signal
However, Deisher teaches of a data router configured to receive the control signal and determine whether to store, in the storage cells of each of the PEs, a corresponding one of the plurality of first data elements or corresponding ones of the plurality of second data elements based on the control signal (paragraph 316-317; where the placement of the weight values and data for the layers are directed into an internal buffer depending on the layer type. In the combination with Nagarakatte and Narayanaswami, the layer type is received via the instruction of Narayanaswami and the internal buffers are internal to the PEs).
Nagarakatte and Narayanaswami are analogous art because they are from the same field of endeavor, as they involve managing weights and inputs for neural network layers.
It would have been obvious to one of ordinary skill in the art having the teachings of Nagarakatte and Narayanaswami before the time of the effective filing of the claimed invention to incorporate the instructions including the layer types in Nagarakatte as taught in Narayanaswami. Their motivation would have been to more efficiently perform the computations for a given layer (Narayanaswami, paragraph 12).
Nagarakatte, Narayanaswami, and Deisher are analogous art because they are from the same field of endeavor, as they involve managing weights and inputs for neural network layers.
It would have been obvious to one of ordinary skill in the art having the teachings of Nagarakatte, Narayanaswami, and Deisher before the time of the effective filing of the claimed invention to incorporate the directing the placement of the data and weights based on the layer type in the combination of Nagarakatte and Narayanaswami as taught in Deisher. Their motivation would have been to provide for more flexibility in the neural network layers.
With respect to claim 12, the combination of Nagarakatte, Narayanaswami, and Deisher teaches of the limitations cited and described above with respect to claim 1 for the same reasoning described with regards to claim 1.
Nagarakatte also teaches of a memory circuit, comprising: an array comprising a plurality of processing elements (PEs) (fig. 4; paragraph 36, 81; where the GEMM is made up of an array of processing elements);
wherein each of the PEs includes a plurality of storage cells (fig. 4; paragraph 36, 81; where the GEMM is made up of an array of processing elements. Each PE includes three FIFO buffers as well as multiple registers).
The combination of Nagarakatte, Narayanaswami, and Deisher teaches of wherein each of the PEs is configured to selectively store, based on a control signal indicating a layer type, (i) a singular one of a plurality of first data elements in one of the corresponding storge cells; or (ii) plural ones of a plurality of second data elements in the corresponding storage cells, respectively (Narayanaswami, fig. 1, 3; paragraph 44, 46; Deisher, paragraph 316-317; In the combination, the placement of the weight values and data for the layers are directed into an internal buffer depending on the layer type received in the instruction that specifies the layer type).
The reasoning for obviousness is the same as indicated above with respect to claim 1.
With respect to claims 2 and 13, Nagarakatte teaches of wherein the first data elements include weight data elements, and the second data elements include input data elements (fig. 4; paragraph 32, 34; SRAM 484 stores the filters/weights and SRAM 482 stores the input feature map (ifmap));
With respect to claims 11 and 18, Nagarakatte teaches of wherein the PEs are each configured to perform at least one multiplication operation on one or more of the plurality of first data elements and one or more of the plurality of second data elements (paragraph 32, 42, 81; where the PEs perform convolution via matrix multiplication on the inputted weights and fmap).
With respect to claim 14, Deisher teaches of a data router configured to receive the control signal and determine whether to store the singular one of the plurality of first data elements or the plural ones of the plurality of second data elements based on the control signal (paragraph 316-317; where the placement of the weight values and data for the layers are directed into an internal buffer depending on the layer type. In the combination with Nagarakatte and Narayanaswami, the layer type is received via the instruction of Narayanaswami and the internal buffers are internal to the PEs).
The reasoning for obviousness is the same as indicated above with respect to claim 1.
With respect to claim 19, the combination of Nagarakatte, Narayanaswami, and Deisher teaches of the limitations cited and described above with respect to claims 1 and 12 for the same reasoning described with regards to claims 1 and 12.
The combination of Nagarakatte, Narayanaswami, and Deisher also teaches of teaches of a method, comprising: identifying a layer type of a neural network for processing a plurality of input data elements and a plurality of weight data elements (Nagarakatte, fig. 4-5; paragraph 32, 34-38, 42-46, 66; Narayanaswami, fig. 3; paragraph 45-46; where instructions can include tensor op codes for a convolution layer or depth-wise convolution layers);
in response to the layer type being a first type, storing a singular one of the plurality of weight data elements in one of a plurality of storage cells of a corresponding processing element (Nagarakatte, fig. 4-5; paragraph 32, 34-38, 42-46, 66; Deisher, paragraph 316-317; where the placement of the weight values and data for the layers are directed into an internal buffer depending on the layer type. In the combination with Nagarakatte and Narayanaswami, the layer type is an input stationary layer that is a weight stationary data flow, each PE receives a weight); and
in response to the layer type being a second type, storing plural ones of the plurality of input data elements in the plurality of storage cells of the corresponding processing element, respectively (Nagarakatte, fig. 4-5; paragraph 32, 34-38, 42-46, 66; Deisher, paragraph 316-317; where the placement of the weight values and data for the layers are directed into an internal buffer depending on the layer type. In the combination with Nagarakatte and Narayanaswami, the layer type is an input stationary layer that is a feature map/input stationary data flow, the PEs receive the feature map).
The reasoning for obviousness is the same as indicated above with respect to claim 1.
With respect to claim 20, Narayanaswami teaches of wherein the first type includes a regular convolutional layer or an attention layer, and the second type includes a depth-wise convolutional layer (fig. 3; paragraph 45-46; where instructions can include tensor op codes for a convolution layer or depth-wise convolution layers).
The reasoning for obviousness is the same as indicated above with respect to claim 1.
Allowable Subject Matter
Claims 3-10, 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Mehendale et al. (US 2024/0104361) discloses a weight multiplexer and a input data multiplexer, where depending on the configuration the multiplexers can select either all or duplicates of half of the weight or input data elements and route them to the MAC engine. See fig. 13; paragraphs 99-104. However, Mehendale does not disclose the multiplexer configuration presented in the present claims 3 or 15.
Lee et al. (US 20230022516) discloses multiplexers that are coupled to sense amplifiers and are used to select a weight value from the memory and output it to the multiply circuitry. See fig. 4; paragraph 32-33. However, Lee does not disclose the multiplexer configuration presented in the present claims 3 or 15.
Yang (US 11,803,756) discloses changing a neural network model based on the dedicated hardware device it is being carried out on. The mode of the neural network model is changed based on if the hardware device is a weight stationary dataflow type or is an output stationary dataflow type. However, Yang does not disclose the multiplexer configuration presented in the present claims 3 or 15.
Nagarakatte et al. (US 2023/0376733) discloses a dynamically reconfigurable general matrix-matrix multiplication block (GEMM block) of processing elements (PEs) that can be configured into a tall array or individual square arrays. This is done by configurint the GEMM block for either an input-stationary dataflow or an output-stationary data flow. The input-stationary dataflow can be a weight stationary dataflow or a feature map stationary dataflow. However, Nagarakatte does not disclose the multiplexer configuration presented in the present claims 3 or 15.
With respect to claim 3, the prior art does not teach or suggest, “wherein the data router includes: a first multiplexer having a first input connected to the second buffer, a second input connected to the first buffer, and a first output connected to an input port of the array; and a second multiplexer having a third input connected to the second buffer, a fourth input connected to the first buffer, and a second output connected to a write port of the array,” in the context of the claims.
With respect to claim 15, the prior does not teach or suggest, “wherein the data router includes: a first multiplexer having a first input configured to receive at least one of the second data elements, a second input configured to receive at least one of the first data elements, and a first output connected to an input port of the array; and a second multiplexer having a third input configured to receive at least one of the second data elements, a fourth input configured to receive at least one of the first data elements, and a second output connected to a write port of the array,” in the context of the claims.
Response to Arguments
Applicant’s arguments, see pages 8-9 of the remarks filed on 12/23/2025, with respect to the rejection(s) of claim(s) 1-2, 11-14, and 18-20 under 35 USC 103 using the Sun reference have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Nagarakatte et al. (US 2023/0376733).
Conclusion
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/Michael Krofcheck/Primary Examiner, Art Unit 2138
MICHAEL C. KROFCHECK
Primary Examiner
Art Unit 2138
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