Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Attorney Docket Number: GFEC2023001-US-NP
Filling Date: 03/13/24
Priority Date: 11/21/23
Inventor: Tang et al
Examiner: Bilkis Jahan
DETAILED ACTION
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-17 in the reply filed on 09/01/26 is acknowledged.
Claims 18-25 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method, there being no allowable generic or linking claim.
Claim Objections
Claim 13 is objected to because of the following informalities:
Claim 13 in line 2 recites “structurer”. However, it should be “structure”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6, 12-13 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Briere (US 2013/0015498 A1).
Regarding claim 1, Briere discloses a semiconductor device (Fig. 5, Paras. 47-50) comprising: a substrate (Para. 4); a semiconductor layer stack 510, 520, 530 on the substrate (Para. 4), the semiconductor layer stack including: a non-silicon channel layer 531 (III-V material); and a barrier layer 533 on the channel layer 531; and a gate 536, a source 532, and a drain 534 formed on or in the semiconductor layer stack, wherein at least one of the substrate (Para. 4) or the semiconductor layer stack includes a diode 512, 514, a first terminal of the diode 512 electrically coupled to the source 532, and a second terminal 514 of the diode electrically coupled to the drain 534.
Regarding claim 2, Briere discloses the semiconductor device of claim 1, wherein: the substrate includes at least one of silicon, silicon carbide, silicon on insulator (SOI) (Para. 4), sapphire, gallium nitride (GaN), engineered GaN, or another semiconductor material having a bandgap wider than a bandgap of silicon; and the channel layer includes at least one of GaN, AlGaN, or InAiN.
Regarding claim 3, Briere discloses the semiconductor device of claim 1, wherein the diode 512, 514 is formed in the substrate (Fig. 5).
Regarding claim 6, Briere discloses the semiconductor device of claim 3, wherein: the substrate includes a p-type semiconductor layer that includes a p+-type region 512 (claim does not specify the concentration) and an N+ region 514 formed therein, the p-type semiconductor layer 512 and the n+-type region 514 forming the diode; the source includes a source contact 543 electrically coupled to the p+-type region 512; and the drain includes a drain contact 543 electrically coupled to the n+-type region 514.
Regarding claim 12, Briere discloses the semiconductor device of claim 1, wherein: the semiconductor layer stack includes a p-type semiconductor layer 512 and an N+ type semiconductor layer 514, the n semiconductor layer 514 and the p-type semiconductor layer 512 forming the diode.
Regarding claim 13, Briere discloses the semiconductor device of claim 12, wherein the semiconductor layer stack further includes a conductive shield structurer 524, 520 (Para. 47, claim 1) between the channel layer 535 and the n+- type semiconductor layer 514.
Regarding claim 15, Briere discloses the semiconductor device of claim 1, wherein: the semiconductor layer stack includes an n-type semiconductor layer 514 and a p+-type semiconductor layer 512, the p+-type semiconductor layer 512 and the n-type semiconductor layer 514 forming the diode.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4, 7, 8-9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Briere (US 2013/0015498 A1) in view of Nagumo et al (US 2016/0056145 A1).
Regarding claim 4, Briere does not explicitly disclose the semiconductor device of claim 3, wherein the substrate includes a p-type semiconductor layer and an n+-type semiconductor layer that form the diode in the substrate, wherein the n+-type semiconductor layer is on a side of the p-type semiconductor layer opposing the channel layer.
However, Nagumo discloses the substrate includes a p-type semiconductor layer SL1 (Fig. 2, Para. 81) and an n+-type semiconductor layer ES (Para. 77, claim does not specify the concentration) that form the diode in the substrate, wherein the n+-type semiconductor layer ES is on a side of the p-type semiconductor layer SL opposing the channel layer CH (Para. 77).
Nagumo teaches the above modification is used to improve frequency of the device (Para. 3). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to substitute Briere’s arrangement of p-type and n-type semiconductor layers with Nagumo arrangement of p-type and n-type semiconductor layers as suggested above to improve frequency of the device (Para. 3).
Regarding claim 7, Nagumo discloses the semiconductor device of claim 3, wherein the substrate includes an n-type semiconductor layer ES and a p-type semiconductor layer SL1, the p-type semiconductor layer SL1 on a side of the n-type semiconductor layer ES opposing the channel layer CH.
Regarding claim 8, Nagumo discloses the semiconductor device of claim 7, wherein the n-type semiconductor layer ES (Para. 114) is an epitaxial layer grown on the p-type semiconductor layer SL1.
Regarding claim 9, Briere does not explicitly disclose the semiconductor device of claim 7, wherein the n-type semiconductor layer has a lower doping density than the p-type semiconductor layer.
However, Nagumo discloses the P-type impurity layer SL1 has impurity concentration is more than 1x1016 (Para. 67). Also, Nagumo discloses N-type layer is just with N-type concentration ES (Paras. 68, 76, claims 12, 13). Therefore, it would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to obtain the n-type semiconductor layer has a lower doping density than the p-type semiconductor layer for low resistance P-type layer (common in the art).
Regarding claim 11, Briere further discloses the semiconductor device of claim 7, wherein: the n-type semiconductor layer 514 includes a p+-type region 511b and an n+-type region 513b formed therein; the source includes a source contact 543 electrically coupled to the p+-type region 511b; and the drain 534 includes a drain contact 543 electrically coupled to the n+-type region 513b.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Briere (US 2013/0015498 A1) in view of Curatola et al (US 9,570,438 B1).
Regarding claim 17, Briere does not explicitly disclose the semiconductor device of claim 1, wherein the diode includes a Schottky diode.
However, Curatola discloses the diode includes a Schottky diode 154 (Fig. 5, col. 10, lines 1-4). Curatola teaches the above modification is used to obtain low bias diode of the device (col. 10, lines 1-4). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to substitute Briere diode with Curatola diose as suggested above to obtain low bias diode of the device (col. 10, lines 1-4).
Allowable Subject Matter
Claims 5, 10, 14 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BILKIS JAHAN whose telephone number is (571)270-5022. The examiner can normally be reached Monday-Friday, 8:00 am-5 Pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon T Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
BILKIS . JAHAN
Primary Examiner
Art Unit 2817
/BILKIS JAHAN/Primary Examiner, Art Unit 2817
Prosecution Insights