Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Richter et al. (US Pub # 2023/0360700).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Richter et al. teach an apparatus, comprising: one or more control circuits configured to connect to a cross-point structure having self-selecting memory cells, each self-selecting memory cell having a threshold switching selector (see Fig. 2-3, 6-7, 9-15 and paragraph 0035-0037, 0039-0040, 0043-0046, 0062-0063, 0084-0097, 0101-0138, 0143-0145, Unit 102 controller, OTS is switching element), the one or more control circuits configured to: write either a first or a second data value to each of a pair of self-selecting memory cells, where, to write one of the data values to a corresponding pair of the self-selecting memory cells, the one or more control circuits are configured to: to write the first data value, apply a write signal with a first polarity to the first of the pair of the self-selecting memory cells and apply the write signal with a second polarity to the second of the pair of the self-selecting memory cells, the second polarity having a first relative polarity with respect to the first polarity (see Fig. 2-3, 6-7, 9-15 and paragraph 0035-0037, 0039-0040, 0043-0046, 0062-0063, 0084-0097, 0101-0138, 0143-0145, step 704, 706, 1502); and to write the second data value, apply the write signal with a polarity opposite the first polarity to the first of the pair of the self-selecting memory cells and apply the write signal with a polarity opposite the second polarity to the second of the pair of the self-selecting memory cells; and subsequent to writing each of the data values to the corresponding pair of self-selecting memory cells, read selected ones of the written pairs of self-selecting memory cells, where, to read a selected one of the written pairs, the one the one or more control circuits are configured to: apply a read signal to each of the pair of self-selecting memory cells having a second relative polarity, the second relative polarity being opposite to the first relative polarity (see Fig. 2-3, 6-7, 9-15 and paragraph 0035-0037, 0039-0040, 0043-0046, 0062-0063, 0084-0097, 0101-0138, 0143-0145, step 704, 708, 1504); and compare a voltage level at a terminal of each of the pair of self-selecting memory cells in response to the applied read signal (see Fig. 2-3, 6-7, 9-15 and paragraph 0035-0037, 0039-0040, 0043-0046, 0062-0063, 0084-0097, 0101-0138, 0143-0145, step 902, 1006, compare with reference voltage).
Even though Richter et al. teach applying first and second programming signal to rpgram as LRS or HRS state but silent exclusively about first and second data values. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Richter et al. where LRS or HRS data state actually also indicate data values in order to properly program / write data into memory cell and to improve read margin (see paragraph 0077).
Regarding claim 2, Richter et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Richter et al. further teach, wherein each of the self-selecting memory cells has a first terminal and a second terminal, and wherein to read the selected pairs of self-selecting memory cells the one or more control circuits are configured to: independently and concurrently apply the read signal to the first terminal of each of the pair of self-selecting memory cells; and to the compare the voltage level at the first terminal of each of the pair of self-selecting memory cells in response to the applied read signal (see Fig. 2-3, 6-7, 9-15 and paragraph 0035-0037, 0039-0040, 0043-0046, 0062-0063, 0084-0097, 0101-0138).
Regarding claim 3, Richter et al. teach all claimed subject matter as applied in prior rejection of claim 2 on which this claim depends.
Richter et al. further teach, wherein to read the selected pairs of self-selecting memory cells the one or more control circuits are configured to compare a relative voltage levels at which the first and the second of the pair of the self-selecting memory cells turn on in response to the applied write signal (see Fig. 2-3, 6-7, 9-15 and paragraph 0035-0037, 0039-0040, 0043-0046, 0062-0063, 0084-0097, 0101-0138, 0143)
Regarding claim 4, Richter et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Richter et al. further teach, wherein each of the self-selecting memory cells has a first terminal and a second terminal, and wherein to read the selected pairs of self-selecting memory cells the one or more control circuits are configured to: concurrently apply the read signal from a common source to the first terminal of each of the pair of self-selecting memory cells; and to the compare the voltage level at the second terminal of each of the pair of self-selecting memory cells in response to the applied read signal (see Fig. 2-3, 6-7, 9-15 and paragraph 0035-0037, 0039-0040, 0043-0046, 0062-0063, 0084-0097, 0101-0138, 0143-0145)
Regarding claim 5, Richter et al. teach all claimed subject matter as applied in prior rejection of claim 4 on which this claim depends.
Richter et al. further teach, wherein to read the selected pairs of self-selecting memory cells the one or more control circuits are configured to compare a relative voltage levels at which one but not the other of the first and the second of the pair of the self-selecting memory cells turn on in response to the applied write signal (see Fig. 2-3, 6-7, 9-15 and paragraph 0035-0037, 0039-0040, 0043-0046, 0062-0063, 0084-0097, 0101-0132)
Regarding claim 6, Richter et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Richter et al. further teach, wherein the write signal is a current and the read signal is a current (see Fig. 2-3, 6-7, 9-15 and paragraph 0035-0037, 0039-0040, 0043-0046, 0062-0063, 0084-0097)
Regarding claim 7, Richter et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Richter et al. further teach, wherein the one or more control circuits are formed on a control die, the apparatus further comprising: a memory die including the cross-point structure, the memory die separate from and bonded to the control die (see Fig. 2-3, 6-7, 9-15 and paragraph 0035-0037, 0039-0040, 0043-0046, 0062-0063, 0084-0097, 0101-0135)
Regarding claim 8, Richter et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Richter et al. further teach, further comprising: the cross-point structure, the one or more control circuits and the cross-point structure formed on a single die (see Fig. 2-3, 6-7, 9-15 and paragraph 0035-0037, 0039-0040, 0043-0046, 0062-0063, 0084-0097, 0101-0110)
Regarding claim 9, Richter et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Richter et al. further teach, further comprising: the cross-point structure, wherein each of the self-selecting memory cells is an Ovonic Threshold Switch (OTS) (see Fig. 2-3, 6-7, 9-15 and paragraph 0035-0037, 0039-0040, 0043-0046, 0062-0063, 0084-0097, 0101-0127)
Regarding claim 10, Richter et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Richter et al. further teach, further comprising: the cross-point structure, wherein the cross-point structure comprises: a plurality of bit lines running in a first direction over a substrate; and a plurality of first word lines running in a second direction over the substrate, and wherein the self-selecting memory cells includes a first plurality of memory cells each having a first terminal connected to a corresponding one of the bit lines and a second terminal connected to a corresponding one of the first word lines (see Fig. 2-3, 6-7, 9-15 and paragraph 0035-0037, 0039-0040, 0043-0046, 0062-0063, 0084-0097)
Regarding claim 11, Richter et al. teach all claimed subject matter as applied in prior rejection of claim 10 on which this claim depends.
Richter et al. further teach, the cross-point structure further comprising: a plurality of second word lines running in the second direction over the substrate, the plurality of bit lines located between the plurality of first word lines and the plurality of second word lines, and wherein the self-selecting memory cells includes a second plurality of memory cells each having a first terminal connected to a corresponding one of the bit lines and a second terminal connected to a corresponding one of the second word lines (see Fig. 2-3, 6-7, 9-15 and paragraph 0035-0037, 0039-0040, 0043-0046, 0062-0063, 0084-0097, 0101)
Regarding claim 12, Richter et al. teach all claimed subject matter as applied in prior rejection of claim 11 on which this claim depends.
Richter et al. further teach, wherein each pair of the self-selecting memory cells comprises a first of the pair having a first terminal connected to a corresponding first bit line and a second terminal connected to a first word line and a second of the pair having a first terminal connected to the corresponding first bit line and a second terminal connected to a second word line (see Fig. 2-3, 6-7, 9-15 and paragraph 0035-0037, 0039-0040, 0043-0046, 0062-0063, 0084-0097, 0101-0124)
Regarding claim 13, Richter et al. teach all claimed subject matter as applied in prior rejection of claim 12 on which this claim depends.
Richter et al. further teach, wherein to read the selected one of the written pairs of self-selecting memory cells the one or more control circuits are further configured to: apply the read signal to the corresponding first bit line (see Fig. 2-3, 6-7, 9-15 and paragraph 0035-0037, 0039-0040, 0043-0046, 0062-0063, 0084-0097, 0101-0130)
Regarding independent claim 14, Richter et al. teach a method, comprising: receiving a plurality of bits of data; programing each bit of the plurality of data bits into a pair of self-selecting memory cells of a cross-point array of a plurality of self-selecting memory cells by (see Fig. 2-3, 6-7, 9-15 and paragraph 0035-0037, 0039-0040, 0043-0046, 0062-0063, 0084-0097, 0101-0138, 0143-0145, Unit 202 array): writing a first value for the bit by applying a write signal with a first polarity to a first of the pair and applying the write signal with a second polarity to a second of the pair, the second polarity having a first relative polarity with respect to the first polarity (see Fig. 2-3, 6-7, 9-15 and paragraph 0035-0037, 0039-0040, 0043-0046, 0062-0063, 0084-0097, 0101-0138, 0143-0145, step 704, 706, 1502); and writing a second value for the bit by applying the write signal with an opposite of the second polarity to the second of the pair and applying the write signal with the opposite of the first polarity to the first of the pair (see Fig. 2-3, 6-7, 9-15 and paragraph 0035-0037, 0039-0040, 0043-0046, 0062-0063, 0084-0097, 0101-0138, 0143-0145, step 704, 708, 1504); and reading the programmed bits of data from the cross-point array, including reading the bit programmed to a selected pair of self-selecting memory cells by: concurrently applying a read signal to the pair with a second relative polarity, the second relative polarity being opposite to the first relative polarity (see Fig. 2-3, 6-7, 9-15 and paragraph 0035-0037, 0039-0040, 0043-0046, 0062-0063, 0084-0097, 0101-0138, 0143-0145, step 902, 1006, compare with reference voltage).
Even though Richter et al. teach applying first and second programming signal to rpgram as LRS or HRS state but silent exclusively about first and second data values. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Richter et al. where LRS or HRS data state actually also indicate data values in order to properly program / write data into memory cell and to improve read margin (see paragraph 0077).
Regarding claim 15, Richter et al. teach all claimed subject matter as applied in prior rejection of claim 14 on which this claim depends.
Richter et al. further teach, wherein the write signal is a current level and the read signal is a current (see Fig. 2-3, 6-7, 9-15 and paragraph 0035-0037, 0039-0040, 0043-0046, 0062-0063, 0084-0097, 0101-0108)
Regarding claim 16, Richter et al. teach all claimed subject matter as applied in prior rejection of claim 14 on which this claim depends.
Richter et al. further teach, wherein each of the self-selecting memory cells has a first terminal and a second terminal, and wherein reading the bit programmed to the selected pair of self-selecting memory cells includes: concurrently applying the read signal from a common source to the first terminal of each of the selected pair; and comparing a voltage level at the second terminal of each of the pair in response to the applied read signal (see Fig. 2-3, 6-7, 9-15 and paragraph 0035-0037, 0039-0040, 0043-0046, 0062-0063, 0084-0097, 0101-0115)
Regarding claim 17, Richter et al. teach all claimed subject matter as applied in prior rejection of claim 16 on which this claim depends.
Richter et al. further teach, wherein the cross-point array comprises: a plurality of bit lines running in a first direction over a substrate; a plurality of first word lines running in a second direction over the substrate; and a plurality of second word lines running in the second direction over the substrate, each pair of the self-selecting memory cells comprising a first of the pair having a first terminal connected to a corresponding first bit line and a second terminal connected to a first word line and a second of the pair having a first terminal connected to the corresponding first bit line and a second terminal connected to a second word line, wherein concurrently applying the read signal from a common source to the first terminal of each of the selected pair includes: applying the read signal to the corresponding first bit line (see Fig. 2-3, 6-7, 9-15 and paragraph 0035-0037, 0039-0040, 0043-0046, 0062-0063, 0084-0097, 0101-0138, 0143-0145)
Regarding claim 18, Richter et al. teach all claimed subject matter as applied in prior rejection of claim 14 on which this claim depends.
Richter et al. further teach, wherein each of the self-selecting memory cells has a first terminal and a second terminal, and wherein reading the bit programmed to the selected pair of self-selecting memory cells includes: independently and concurrently applying the read signal the first terminal of each of the selected pair; and comparing a voltage level at the first terminal of each of the pair in response to the applied read signal (see Fig. 2-3, 6-7, 9-15 and paragraph 0035-0037, 0039-0040, 0043-0046, 0062-0063, 0084-0097, 0101-0107)
Regarding independent claim 19, Richter et al. teach a memory system, comprising: a cross-point memory structure having a plurality of bit lines, a plurality of word lines, and a plurality memory cells, each memory cell connected at a junction of one of the bit lines and one of the word lines, each memory cell having a threshold switching selector; and one or more control circuits in communication with the cross-point memory structure and configured to program data to and to read data from the cross-point memory structure (see Fig. 2-3, 6-7, 9-15 and paragraph 0035-0037, 0039-0040, 0043-0046, 0062-0063, 0084-0097, 0101-0138, 0143-0145, Unit 102 controller, OTS is switching element), each bit of a plurality of data bits being stored in a pair of the memory cells, where to program each data bit into a pair of the memory cells the one or more control circuits are configured to: write a first value for the bit by applying a write current with a first polarity to a first of the pair (see Fig. 2-3, 6-7, 9-15 and paragraph 0035-0037, 0039-0040, 0043-0046, 0062-0063, 0084-0097, 0101-0138, 0143-0145, step 704, 706, 1502) and applying the write current with a second polarity having first relative polarity to a second of the pair; and write a second value for the bit by applying the write current with the first polarity to second of the pair and applying the write current with the second polarity to the first of the pair (see Fig. 2-3, 6-7, 9-15 and paragraph 0035-0037, 0039-0040, 0043-0046, 0062-0063, 0084-0097, 0101-0138, 0143-0145, step 704, 708, 1504); and where to read a data bit from a selected pair of memory cells the one or more control circuits are configured to: concurrently apply a read current with a second relative polarity different to the first relative polarity to the selected pair (see Fig. 2-3, 6-7, 9-15 and paragraph 0035-0037, 0039-0040, 0043-0046, 0062-0063, 0084-0097, 0101-0138, 0143-0145, step 902, 1006, compare with reference voltage).
Even though Richter et al. teach applying first and second programming signal to rpgram as LRS or HRS state but silent exclusively about first and second data values. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Richter et al. where LRS or HRS data state actually also indicate data values in order to properly program / write data into memory cell and to improve read margin (see paragraph 0077).
Regarding claim 20, Richter et al. teach all claimed subject matter as applied in prior rejection of claim 19 on which this claim depends.
Richter et al. further teach, wherein the plurality of word lines comprises a plurality of first word lines and a plurality of second word lines, each pair of the memory cells storing a data bit comprising a first of the pair having a first terminal connected to a corresponding first bit line and a second terminal connected to one of first word lines and a second of the pair having a first terminal connected to the corresponding first bit line and a second terminal connected to one of the second word lines, wherein, to concurrently apply the read current to both of the pair, the one or more control circuits are further configured to: apply the read current to the corresponding first bit line (see Fig. 2-3, 6-7, 9-15 and paragraph 0035-0037, 0039-0040, 0043-0046, 0062-0063, 0084-0097, 0101-0138)
Response to Arguments
Applicant's arguments filed 03/16/2026 have been fully considered but they are not persuasive.
Because, both assignee and inventors are different but if they still co-own (as applicant argued), applicant need to provide ownership document for Richter et al. reference.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277 and fax number is (571)273-2908. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
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