CTFR 18/757,206 CTFR 82195 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1, 4-11, 13, 14, 17, 18 and 20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Lattimore et al. (Patent No.: US 6,353,558) . Regarding independent claims 1, 14 and 20 , Lattimore discloses a computer-implemented method for controlling cache memory accesses, the method comprising: transmitting a first clock signal (Fig.1 and Fig.5: first clock signal C2) to the cache memory (Fig.1: memory array 110), wherein a first rising edge (Fig.5: see the first rising edge of C2) of the first clock signal (Fig.5: first clock signal C2) asserts a word line (Fig.5: see WORDLINE 114) and asserts a second clock signal (Fig.5 and col.7, lines 30-38: address signal 132 is asserted when clock signal C2 is asserted and that a wordline signal is asserted responsive to clock signal C2 being asserted and the asserted wordline signal and asserted clock signal C1 are concurrently present during operation of the write wordline generator); and transmitting a second clock signal (Fig.1 and Fig.5: second clock signal C1) to the cache memory (Fig.1: memory array 110), wherein a first rising edge (Fig.5: see the first rising edge of C1) of the second clock signal (Fig.5: second clock signal C1 ) precedes a second rising edge (Fig.5: see the second rising edge of C2) of the first clock signal (Fig.5: see the first rising edge of C2), and the first rising edge of the second clock signal de-asserts the word line (col.7, lines 27-57: Referring now to FIG. 5, selected signals are shown in the context of their timing and interdependence to illustrate the embodiments of FIGS. 1, 2 and 3. Clock signal C2 is shown, with its alternating first and second phases indicated. Clock signal C1 is used for clocking the write wordline generator 300 and write column generator 400. Address signal 132 is shown asserted when clock C2 is asserted. This signal 132 is input to address decoder 130 of FIG. 1. Also responsive to clock C2 being asserted a wordline signal is asserted on the wordline 114 for the corresponding write wordline generator 300. The wordline 114 is asserted responsive to decoding the address signal 132. Responsive to the wordline signal being asserted and clock C1 being asserted, the output voltage on the output 316 of the logic circuitry 310 is pulled down through FET's N3 and N4, which also pulls up the output voltage on node 324 of latch circuitry 320 through inverter I118. This node 324 is held up through FET's P1, N88 and N4 until another occurrence of phase one of the clock C2 (when clock C1 is deasserted). Next, the wordline signal is deasserted responsive to the clock C2 signal being deasserted. Responsive to the wordline signal on wordline 114 transitioning from being asserted to being not asserted, and the output signal on node 324 being asserted, the write wordline signal on output node 336 is triggered through NAND gate G131. Further, the write wordline signal on node 336 continues to be held up due to the latch circuitry 320., until clock signal C1 is next deasserted.). Regarding claim 4 , Lattimore teaches wherein the cache memory comprises an L3 cache (col.8, lines 4-36). Regarding claim 5 , Lattimore teaches wherein the cache memory comprises an L2 cache (col.8, lines 4-36). Regarding claims 6 and 17 , Lattimore teaches wherein a memory controller includes logic to generate the second clock signal from the first clock signal (Fig.5: second clock signal C1 is generated based on the first clock signal C2). Regarding claim 7 , Lattimore teaches wherein the logic includes at least one of a flip-flop circuit or a delay circuit (second clock signal C1 is reversed against the first clock signal C2. Thus, flip-flop circuit is used). Regarding claim 8 , Lattimore teaches wherein the cache memory is included within an instruction pipeline (col.1, lines 20-35). Regarding claim 9 , Lattimore teaches wherein the cache memory comprises at least four bit columns (col.3, lines 23-28). Regarding claim 10 , Lattimore teaches transmitting a column select signal to the cache memory, wherein the column select signal asserts a subset of bit columns included in the at least four bit columns (Fig.1 and Fig.5). Regarding claims 11 and 18 , Lattimore teaches wherein the first rising edge of the second clock signal enables a sense amplifier to sense a pair of bit lines connected to a bit cell enabled by the word line (Fig.5). Regarding claim 13 , Lattimore teaches driving a data signal to at least one bit cell enabled by the word line (Fig.1 and Fig.5) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 2, 3, 12, 15, 16 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reasons for allowance: Claim 2 identifies the distinct features “wherein the first clock signal is transmitted by a first clock that comprises a conventional clock, and the second clock signal is transmitted by a second clock that comprises a self-timing clock", which are not taught or suggested by the prior art of records. Claim 3 , which respectively depends on objected-to claim 2 , are allowable for at least the same reasons as claim 2. Claim 12 identifies the distinct features “wherein the sense amplifier latches a data value, determined from sensing the pair of bit lines, until the second rising edge of the first clock signal occurs, and further comprising determining a data value based on the pair of bit lines while the data value is latched", which are not taught or suggested by the prior art of records. Claim 15 identifies the distinct features “wherein the first clock signal is transmitted by a first clock that comprises a conventional clock, and the second clock signal is transmitted by a second clock that comprises a self-timing clock", which are not taught or suggested by the prior art of records. Claim 16 , which respectively depends on objected-to claim 15 , are allowable for at least the same reasons as claim 15. Claim 19 identifies the distinct features “wherein the sense amplifier latches a data value, determined from sensing the pair of bit lines, until the second rising edge of the first clock signal occurs, and further comprising determining a data value based on the pair of bit lines while the data value is latched", which are not taught or suggested by the prior art of records. Claims 2, 3, 12, 15, 16 and 19 would be allowable over the prior art of record because the claimed features as mentioned above in combination with other claimed features are not recited or suggested by the prior art of records. Response to Arguments 07-37 AIA Applicant’s arguments filed on 05/20/2026 have been fully considered but they are not persuasive. 1 st Point of Argument Regarding Applicant’s remarks on page 8, the applicants argue that Lattimore does not specifically teach the amended limitation that “a first rising edge of the first clock signal asserts a word line and asserts a second clock signal. In response, Examiner disagrees. Claim 1 does not recite that the first clock signal generates or derives the second clock signal. Under the BRI, the claim requires only that the first clock signal asserts the word line and that the second clock signal be asserted in the disclosed timing relationship. Lattimore teaches that address signal 132 is asserted when clock signal C2 is asserted and that a wordline signal is asserted responsive to clock signal C2 being asserted (Fig.5 and col.7, lines 30-34). Lattimore further teaches that the asserted wordline signal and asserted clock signal C1 are concurrently present during operation of the write wordline generator (Fig.5 and col.7, lines 35-38). Thus, Lattimore teaches assertion of the wordline responsive to the first clock signal and assertion of the second clock signal within the timing sequence shown in Fig.5 . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Phan et al. (Patent No.: US 6,671,842) “Asynchronous Bist For Embedded Multiport Memories” Considered for teachings related to the field of digital electronic memory devices, and in particular a method and apparatus for testing embedded asynchronous multiport memories. Does not disclose or suggest the method comprising: transmitting a first clock signal to the cache memory, wherein a first rising edge of the first clock signal asserts a word line and asserts a second clock signal; and transmitting the second clock signal to the cache memory, wherein a first rising edge of the second clock signal precedes a second rising edge of the first clock signal, and the first rising edge of the second clock signal de- asserts the word line . 07-39 AIA THIS ACTION IS MADE FINAL . Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. 07-100 AIA Any inquiry concerning this communication should be directed to Yong Choe at telephone number 571-270-1053 or email to yong.choe@uspto.gov . The examiner can normally be reached on M-F 8:00am to 5:00pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rutz, Jared Ian can be reached on (571) 272-5535 . Any inquiry of a general nature or relating to the status of this application should be directed to the TC 2100 whose telephone number is (571) 272-2100 . Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PMR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-irect.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /YONG J CHOE/Primary Examiner, Art Unit 2135 Application/Control Number: 18/757,206 Page 2 Art Unit: 2135 Application/Control Number: 18/757,206 Page 3 Art Unit: 2135 Application/Control Number: 18/757,206 Page 4 Art Unit: 2135 Application/Control Number: 18/757,206 Page 5 Art Unit: 2135 Application/Control Number: 18/757,206 Page 6 Art Unit: 2135 Application/Control Number: 18/757,206 Page 7 Art Unit: 2135
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