DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on January 17, 2025 is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6 and 11-15 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Gorman et al. (US 8,872,322 B2).
Gorman et al. teaches a stacked chip module with integrated circuit chips comprising:
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With regard to claim 1, a semiconductor package (FIG. 1, stacked chip module 100) comprising: a plurality of integrated circuit (IC) substrates (FIG. 1, substrates 105 of integrated circuit chips 101a-101n) stacked one above another (FIG. 1); and a conductive structure (FIGS. 2 and 3, through-substrate base plate channels 131, 132 and 182) penetrating through the IC substrates (FIG. 1, substrates 105 of integrated circuit chips 101a-101n), wherein each of the IC substrates (FIG. 1, substrates 105 of integrated circuit chips 101a-101n) comprises an identification circuit (FIG. 1, enumerating circuit 180) coupled to the conductive structure (FIGS. 2 and 3, through-substrate base plate channels 131, 132 and 182), and each identification circuit (FIG. 1, enumerating circuit 180) is configured to identify a corresponding IC substrate (FIG. 1, substrate 105 of each integrated circuit chips 101a-101n) by receiving an input signal (FIG. 3 in view of FIG. 1, enumeration signal 185) from the conductive structure (FIGS. 2 and 3, through-substrate base plate channels 131, 132 and 182) and accordingly generating an identifier (FIG. 4 in view of FIG. 3, first control signal 191 and second control signal 192) of the corresponding IC substrate (FIG. 1, substrate 105 of each integrated circuit chips 101a-101n) (For more details, please read: Abstract; from column 1, line 64 to column 3, line 13; and from column 4, line 36 to column 9, line 5).
With regard to claim 2, respective identification circuits (FIG. 1, enumerating circuits 180) of the IC substrates (FIG. 1, substrates 105 of integrated circuit chips 101a-101n) are configured to generate respective identifiers (FIG. 4 in view of FIG. 3, first control signal 191 and second control signal 192 from respective enumerating circuits 180) sequentially in a spatial arrangement order of the IC substrates (FIG. 3 in view of FIG. 1, substrates 105 of integrated circuit chips 101a-101n) (Column 7, lines 4-43) (For more details, please read: Abstract; from column 1, line 64 to column 3, line 13; and from column 4, line 36 to column 9, line 5).
With regard to claim 3, the IC substrates (FIG. 1, substrates 105 of integrated circuit chips 101a-101n) comprises: a first IC substrate (FIG. 1, substrate 105 of one of the integrated circuit chips 101a-101n), wherein when the input signal indicates an address corresponding to the identifier (FIG. 4 in view of FIG. 3, first control signal 191 and second control signal 192) of the first IC substrate (FIG. 1, substrate 105 of one of the integrated circuit chips 101a-101n), the identification circuit (FIG. 1, enumerating circuit 180) of the first IC substrate (FIG. 1, substrate 105 of one of the integrated circuit chips 101a-101n) is configured to send a stimulus signal when receiving the input signal; and a second IC substrate (FIG. 1, substrate 105 of another one of the integrated circuit chips 101a-101n) adjacent to the first IC substrate (FIG. 1, substrate 105 of one of the integrated circuit chips 101a-101n), the identification circuit (FIG. 1, enumerating circuit 180) of the second IC substrate (FIG. 1, substrate 105 of another one of the integrated circuit chips 101a-101n) is configured to receive the stimulus signal and generate the identifier (FIG. 4 in view of FIG. 3, first control signal 191 and second control signal 192) of the second IC substrate (FIG. 1, substrate 105 of another one of the integrated circuit chips 101a-101n) (Column 7, lines 4-43) (For more details, please read: Abstract; from column 1, line 64 to column 3, line 13; and from column 4, line 36 to column 9, line 5).
With regard to claim 6, the identification circuit (FIG. 1, enumerating circuit 180) of the first IC substrate (FIG. 1, substrate 105 of one of the integrated circuit chips 101a-101n) comprises: a storage device (FIG. 4 in view of FIG. 3, register 186), configured to store the identifier (FIG. 4 in view of FIG. 3, first control signal 191 and second control signal 192) of the first IC substrate (FIG. 1, substrate 105 of one of the integrated circuit chips 101a-101n); a coupling circuit (FIG. 3, latch 183), configured to generate the stimulus signal according to a drive signal (FIG. 3 in view of FIG. 1, enumeration signal 185); and a processing circuit (FIG. 3 in view of FIG. 1, counter 181 and register 186), coupled to the storage device (FIG. 4 in view of FIG. 3, register 186) and the coupling circuit (FIG. 3, latch 183), the processing circuit (FIG. 3 in view of FIG. 1, counter 181 and register 186) being configured to generate the drive signal (FIG. 3 in view of FIG. 1, enumeration signal 185) by determining whether the input signal indicates the address corresponding to the identifier (FIG. 4 in view of FIG. 3, first control signal 191 and second control signal 192) of the first IC substrate (FIG. 1, substrate 105 of one of the integrated circuit chips 101a-101n) (Column 7, lines 4-43) (For more details, please read: Abstract; from column 1, line 64 to column 3, line 13; and from column 4, line 36 to column 9, line 5).
With regard to claim 11, the IC substrates (FIG. 1, substrates 105 of integrated circuit chips 101a-101n) comprises: a first IC substrate (FIG. 1, substrate 105 of one of the integrated circuit chips 101a-101n); and a plurality of second IC substrates (FIG. 1, substrate 105 of the other ones of the integrated circuit chips 101a-101n) identical to each other, each second IC substrate (FIG. 1, substrate 105 of another one of the integrated circuit chips 101a-101n) being non-identical to the first IC substrate (FIG. 1, substrate 105 of one of the integrated circuit chips 101a-101n), wherein the identification circuit (FIG. 1, enumerating circuit 180) of the first IC substrate (FIG. 1, substrate 105 of one of the integrated circuit chips 101a-101n) is configured to identify the identifier (FIG. 4 in view of FIG. 3, first control signal 191 and second control signal 192) of the first IC substrate (FIG. 1, substrate 105 of one of the integrated circuit chips 101a-101n) before any of the second IC substrate (FIG. 1, substrate 105 of the other ones of the integrated circuit chips 101a-101n)s (FIG. 1, substrates 105 of integrated circuit chips 101a-101n) is identified (Column 5, lines 22-42 and column 9, lines 11-47) (For more details, please read: Abstract; from column 1, line 64 to column 3, line 13; and from column 4, line 36 to column 9, line 5). It is clearly seen in column 5, lines 22-42 and column 9, lines 11-47 and FIGS. 1 and 2 that the interconnect structure 130 (e.g., using multiplexer 136-138 and through base plate channel 131-132) located in a substrate 105 on each chip 101a-101n may include a combination of different types of interconnect structures (emphasis added); that is, it is a desirable design choice and/or an intended use to configure “a plurality of second IC substrates identical to each other, each second IC substrate being non-identical to the first IC substrate”.
With regard to claim 12, a control circuit (FIGS. 2 and 3, first controller 111 and second controller 112), coupled to the conductive structure (FIGS. 2 and 3, through-substrate base plate channels 131, 132 and 182), the control circuit (FIGS. 2 and 3, first controller 111 and second controller 112) being configured to send the input signal to the conductive structure (FIGS. 2 and 3, through-substrate base plate channels 131, 132 and 182), wherein the control circuit (FIGS. 2 and 3, first controller 111 and second controller 112) is located in one of the IC substrates (FIG. 1, substrates 105 of integrated circuit chips 101a-101n), or located outside the IC substrates (FIG. 1, substrates 105 of integrated circuit chips 101a-101n) (From column 5, line 60 to column 8, line 52).
With regard to claim 13, each of the IC substrates (FIG. 1, substrates 105 of integrated circuit chips 101a-101n) is dynamic random-access memory (Column 9, lines 11-47).
With regard to claim 14, the IC substrates (FIG. 1, substrates 105 of integrated circuit chips 101a-101n) are identical to each other (FIG. 1, and from column 1, line 64 to column 2, line 3).
With regard to claim 15, at least one of the IC substrates (FIG. 1, substrates 105 of integrated circuit chips 101a-101n) is non-identical to the other IC substrates (FIG. 1, substrates 105 of integrated circuit chips 101a-101n) (Column 5, lines 22-42 and column 9, lines 11-47) (For more details, please read: Abstract; from column 1, line 64 to column 3, line 13; and from column 4, line 36 to column 9, line 5). It is clearly seen in column 5, lines 22-42 and column 9, lines 11-47 and FIGS. 1 and 2 that the interconnect structure 130 (e.g., using multiplexer 136-138 and through base plate channel 131-132) located in a substrate 105 on each chip 101a-101n may include a combination of different types of interconnect structures (emphasis added); that is, it is a desirable design choice and/or an intended use to configure “a plurality of second IC substrates identical to each other, each second IC substrate being non-identical to the first IC substrate”.
Allowable Subject Matter
Claims 16-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
With regard to claim 16, the prior art does not teach, suggest or render obvious the claimed method for identifying integrated circuit (IC) substrates in a stack in combination as claimed including:
When each of the IC substrates is in a non-selectable state, turning a first IC substrate of the IC substrates from the non-selectable state to a selectable state by assigning a first identifier to the first IC substrate;
Applying an input signal to a conductive structure penetrating through the IC substrates in the stack; and
Identifying a second IC substrate of the IC substrates by referring the input signal and generating a second identifier, wherein the second IC substrate is adjacent to the first IC substrate.
With regard to claims 17-20, these claims are allowed at least by virtue of their dependencies directly or indirectly from the base claim.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 4, 5 and 7-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicants’ attention is invited to the followings whose inventions disclose similar devices.
Matsuoka et al. (JP 2010-093199 A) teaches a method of manufacturing a laminated semiconductor device.
Kamins (KR 10-1421665 B1) teaches a methods of forming through-substrate interconnects.
CONTACT INFORMATION
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI-AN D. NGUYEN whose telephone number is (571) 272-2170. The examiner can normally be reached MON-THURS (7:00 AM - 5:00 PM).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LEE E. RODAK can be reached at 571-270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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HOAI-AN D. NGUYEN
Primary Examiner
Art Unit 2858
/HOAI-AN D. NGUYEN/ Primary Examiner, Art Unit 2858
Prosecution Insights