Prosecution Insights
Last updated: October 27, 2026
Application No. 18/757,525

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Final Rejection §102
Filed
Jun 28, 2024
Priority
Jun 21, 2019 — TW 108121622 +3 more
Examiner
LEE, CHEUNG
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
United Microelectronics Corp.
OA Round
2 (Final)
92%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
1081 granted / 1172 resolved
+24.2% vs TC avg
Minimal +4% lift
Without
With
+4.2%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
16 currently pending
Career history
1185
Total Applications
across all art units

Statute-Specific Performance

§101
1.9%
-38.1% vs TC avg
§103
42.7%
+2.7% vs TC avg
§102
31.4%
-8.6% vs TC avg
§112
13.4%
-26.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1172 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Terminal Disclaimer The terminal disclaimer filed on September 3, 2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of US Pat. 11,791,203 has been reviewed and is accepted. The terminal disclaimer has been recorded. In view of applicant’s terminal disclaimer filed on September 3, 2026, the rejections of claims 1-6 under nonstatutory double patenting as stated in the Office Action mailed on June 24, 2026 have been withdrawn Response to Amendment In view of applicant’s amendments and arguments filed on September 3, 2026, the objection of the title, and the rejection of claim 1 under 35 U.S.C. 101 statutory double patenting as stated in the Office Action mailed on June 24, 2026 have been withdrawn. Claims 1 and 6 were previously rejected under 35 U.S.C. 102(a)(1) as being anticipated by Song et al. (US Pub. 2013/0001796). This rejection is still maintained. See below for Rejection - 35 U.S.C. 102(a)(1) and Response to Arguments. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Song (US Pub. 2013/0001796; hereinafter “Song”). Regarding Claim 1, Song discloses a method for fabricating semiconductor device, comprising: forming a first inter-metal dielectric (IMD) layer 40 (page 6, paragraph 105) on a substrate 10 (see fig. 5A); forming a first metal interconnection (84, 88) (page 7, paragraph 126) in the first IMD layer 40 (see fig. 5J); removing part of the first IMD layer 40 (page 6, paragraph 116; see fig. 5G); forming a spacer (94, 98) (page 7, paragraph 120) adjacent to the first metal interconnection (84, 88) (see figs. 5I and 5J), wherein an inner sidewall of the spacer (94, 98) comprises an inclined sidewall (see fig. 5J) and a bottom surface of the spacer (94, 98) is even with a top surface of the first IMD layer 40 adjacent to the spacer (94, 98) (a top surface TS1 of a convex portion CVP of the first IMD layer 40 is even with the bottom surface of the spacer 94, 98; see fig. 5J); forming a second IMD layer 100 (page 7, paragraph 133) on the spacer (94, 98) and the first metal interconnection (84, 88) and directly contacting the first IMD layer 40 (page 7, paragraph 133; see fig. 5M); and forming a second metal interconnection (153, 156, 159) (page 8, paragraph 150) in the second IMD layer 100 (see fig. 5T) and on the spacer (94, 98) and the first metal interconnection (84, 88) (a middle second metal interconnection 156 is formed on the spacers 94, 98, and left and right second metal interconnections 153, 159 are formed on the first metal interconnections 84, 88; see fig. 5T), wherein a sidewall of the second metal interconnection 156 is aligned with a sidewall of the spacer (94, 98) (the middle second metal interconnection 156 is aligned with outer sidewalls of the spacers 94, 98; see fig. 5T). Regarding Claim 6, Song discloses wherein the second metal interconnection (153, 156, 159) contacts the spacer (94, 98) and the first metal interconnection (84, 88) directly (see fig. 5T). Allowable Subject Matter Claims 2-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Claim 2 recites the step of forming the second IMD layer comprises: forming a first dielectric layer on the first IMD layer; forming a second dielectric layer on the first dielectric layer; and forming a third dielectric layer on the second dielectric layer. These features in combination with the other elements of the base claim are neither disclosed nor suggested by the prior art of record. Claims 3-5 depend from claim 2, so they are objected for the same reason. Response to Arguments Applicant’s arguments with regard to the rejections under 35 U.S.C. 102(a)(1) has been fully considered, but they are not deemed to be persuasive for at least the following reasons. With regard to the pending 35 USC § 102(a)(1) rejection, applicant presents the following arguments: Claim 1 has been amended to specify forming a spacer adjacent to the first metal interconnection, wherein an inner sidewall of the spacer comprises an inclined sidewall and a bottom surface of the spacer is even with a top surface of the first IMD layer adjacent to the spacer. The amended feature is supported in Fig. 3 of the instant application showing the feature of forming a spacer (24) adjacent to the first metal interconnection (18), wherein an inner sidewall of the spacer comprises an inclined sidewall and a bottom surface of the spacer is even with a top surface of the first IMD layer (16) adjacent to the spacer. Song in Fig. 5J of the cited reference discloses the step of forming a spacer (94, 98) adjacent to the first metal interconnection (84, 88). Song however fails to disclose an inner sidewall of the spacer comprises an inclined sidewall and a bottom surface of the spacer is even with a top surface of the first IMD layer adjacent to the spacer, as recited in the amended claim 1 of the present invention. Instead, the bottom surface of the spacer (94, 98) is clearly higher than the top surface of the first IMD layer (40) adjacent to the spacer. However, Song discloses an inclined inner sidewall of the spacer (94, 98). Specifically, the first metal interconnection (84, 88) has an inclined sidewall, and the spacer (94, 98) is disposed in contact with the inclined sidewall of the first metal interconnection (84, 88). Thus, the inner sidewall of the spacer (94, 98) follows the inclined sidewall of the first metal interconnection (84, 88) and is likewise inclined. Further, as shown in FIG. 5J, the lower insulating film 40 has at least two distinct upper surfaces, including a first upper surface TS1 corresponding to the convex portion CVP and a second upper surface TS2 corresponding to the concave portion CCP1 (page 3, paragraphs 67 and 68). The first upper surface TS1 of the lower insulating film 40 is at the same vertical level as the bottom surface of the spacer (94, 98). The specification further identifies the interface between the first upper surface TS1 of the lower insulating film 40 and the lower surface of spacer 94 as a “fourth boundary surface” (page 1, paragraph 21; page 4, paragraph 82). Accordingly, the first upper surface TS1 corresponds to the top surface of the lower insulating film 40 adjacent to the spacer (94, 98). As illustrated in FIG. 5J, the first upper surface TS1 and the bottom surface of the spacer (94, 98) are at the same vertical level and are therefore coplanar. Thus, Song teaches that the bottom surface of the spacer (94, 98) is even with the top surface of the first IMD layer 40 adjacent to the spacer (94, 98). Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEUNG LEE whose telephone number is (571)272-5977. The examiner can normally be reached 9 AM - 5:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHEUNG LEE/Primary Examiner, Art Unit 2812 September 23, 2026
Read full office action

Prosecution Timeline

Jun 28, 2024
Application Filed
Jun 24, 2026
Non-Final Rejection mailed — §102
Sep 03, 2026
Response Filed
Sep 28, 2026
Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
92%
Grant Probability
96%
With Interview (+4.2%)
1y 10m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1172 resolved cases by this examiner. Grant probability derived from career allowance rate.

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