Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chetlur et al (US 20220115316).
Chetlur et al teaches
[claim 1] A semiconductor structure, comprising: a semiconductor substrate with an original surface (figure 2A, paragraph 0042, where element 202 is the substrate with an original surface [note: original here is defined as inherent to the substrate and not added later, thus a formed substrate has original surfaces]),
a semiconductor island formed based on the semiconductor substrate (figure 2A, paragraph 0042, where element 216A is the semiconductor island formed on the semiconductor substrate [note: “on” has a broad meaning, including have layers between the reference and origin),
a shallow trench isolation (STI) region surrounding the semiconductor island (figure 2A, paragraph 0042, where element 214A is the shallow trench isolation region and surrounds the semiconductor island [element 216A], note that element 214A is an isolation region which surrounds the silicon island [element 216A] and functions similarly to a shallow trench isolation region);
a first buried layer being a localized layer under the semiconductor island, wherein a material of the first buried layer is different from that of the semiconductor substrate (figure 2A, paragraph 0042, where element 208 is the first buried layer and is localized under the silicon island and is different from the substrate [note: the word “localized” is interpreted as contains but not bound to a certain area, the word “different” is interpreted as a different layer/location/place – the buried layer is not the same layer or same thing as the substrate, hence it is “different.”]);
and a second buried layer being a localized layer under the first buried layer, wherein a material of the second buried layer is different from that of the semiconductor substrate (figure 2A, paragraph 0042, where element 204 is the second buried layer and is localized under the silicon island and is different from the substrate [note: the word “localized” is interpreted as contains but not bound to a certain area, the word “different” is interpreted as a different layer/location/place – the buried layer is not the same layer or same thing as the substrate, hence it is “different.”]);
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 6, and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chetlur et al (US 20220115316).
Chetlur et al teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 2] The semiconductor structure in claim 1, wherein the material of the second buried layer is different from that of the first buried layer.
[claim 6] The semiconductor structure in claim 1, wherein a thermal conductivity of the second buried layer is higher than that of the semiconductor substrate.
However, according to MPEP 2144.05 II. ROUTINE OPTIMIZATION
A. Optimization Within Prior Art Conditions or Through Routine Experimentation
Generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages."); In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969) (Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions.). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 809, 10 USPQ2d 1843, 1848 (Fed. Cir. 1989), cert. denied, 493 U.S. 975 (1989)(Claimed ratios were obvious as being reached by routine procedures and producing predictable results); In re Kulling, 897 F.2d 1147, 1149, 14 USPQ2d 1056, 1058 (Fed. Cir. 1990)(Claimed amount of wash solution was found to be unpatentable as a matter of routine optimization in the pertinent art, further supported by the prior art disclosure of the need to avoid undue amounts of wash solution); and In re Geisler, 116 F.3d 1465, 1470, 43 USPQ2d 1362, 1366 (Fed. Cir. 1997)(Claims were unpatentable because appellants failed to submit evidence of criticality to demonstrate that that the wear resistance of the protective layer in the claimed thickness range of 50-100 Angstroms was "unexpectedly good"); Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree "will not sustain a patent"); In re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions."). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416, 82 USPQ2d 1385, 1395 (2007) (identifying "the need for caution in granting a patent based on the combination of elements found in the prior art.").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Chetlur et al to make the buried layer out of material with a thermal conductivity of one of three values, less than, equal to or greater than the thermal conductivity of the substrate. According to the specific needs of the device, and through routine optimization it would be obvious to try all three to maximize the performance of the particular device.
Regarding claim 7
Chetlur et al teaches
[claim 7] A semiconductor structure, comprising: a semiconductor substrate with an original surface (figure 2A, paragraph 0042, where element 202 is the substrate with an original surface [note: original here is defined as inherent to the substrate and not added later, thus a formed substrate has original surfaces]);
a semiconductor island formed based on the semiconductor substrate (figure 2A, paragraph 0042, where element 216A is the semiconductor island formed on the semiconductor substrate [note: “on” has a broad meaning, including have layers between the reference and origin);
a shallow trench isolation (STI) region surrounding the semiconductor island (figure 2A, paragraph 0042, where element 214A is the shallow trench isolation region and surrounds the semiconductor island [element 216A], note that element 214A is an isolation region which surrounds the silicon island [element 216A] and functions similarly to a shallow trench isolation region);
and a buried layer under the semiconductor island (figure 2A, paragraph 0042, where element 208 is the buried layer and under the semiconductor island [element 216A]).
However, Chetlur et al does not specifically disclose
[claim 7] wherein thermal conductivity of the buried layer is higher than that of the semiconductor substrate.
However, according to MPEP 2144.05 II. ROUTINE OPTIMIZATION
A. Optimization Within Prior Art Conditions or Through Routine Experimentation
Generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages."); In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969) (Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions.). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 809, 10 USPQ2d 1843, 1848 (Fed. Cir. 1989), cert. denied, 493 U.S. 975 (1989)(Claimed ratios were obvious as being reached by routine procedures and producing predictable results); In re Kulling, 897 F.2d 1147, 1149, 14 USPQ2d 1056, 1058 (Fed. Cir. 1990)(Claimed amount of wash solution was found to be unpatentable as a matter of routine optimization in the pertinent art, further supported by the prior art disclosure of the need to avoid undue amounts of wash solution); and In re Geisler, 116 F.3d 1465, 1470, 43 USPQ2d 1362, 1366 (Fed. Cir. 1997)(Claims were unpatentable because appellants failed to submit evidence of criticality to demonstrate that that the wear resistance of the protective layer in the claimed thickness range of 50-100 Angstroms was "unexpectedly good"); Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree "will not sustain a patent"); In re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions."). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416, 82 USPQ2d 1385, 1395 (2007) (identifying "the need for caution in granting a patent based on the combination of elements found in the prior art.").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Chetlur et al to make the buried layer out of material with a thermal conductivity of one of three values, less than, equal to or greater than the thermal conductivity of the substrate. According to the specific needs of the device, and through routine optimization it would be obvious to try all three to maximize the performance of the particular device. Noting that Chetlur et al. does not clearly describe the composition of the layers (besides silicon) and paragraph 27 describes the substrate of being able to be many different types, so one could easily experiment with materials having high and low thermal conductivities.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chetlur et al (US 20220115316) in view of Or-Bach et al (US 20230268321).
Chetlur et al teaches all of the limitations of the parent claim, claim 1 but does not specifically disclose
[claim 3] The semiconductor structure in claim 2, wherein the first buried layer is a buried insulator layer, and the second buried layer is a metal containing layer.
Howeer, Or-Bach et al does teach
[claim 3] The semiconductor structure in claim 2, wherein the first buried layer is a buried insulator layer, and the second buried layer is a metal containing layer (figure 2, paragraph 0062, where element 0206 is the first buried layer under the island [element 0216 surrounded by element 0222], and is a dielectric layer. Element 0208 is the second buried layer is made of metal).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Chetlur et al as modified to incorporate the teachings of Or-Bach et al in order to have the buried layers be different in material and function to allow for a conductive path in the buried layer to contact other portions of a circuit while keeping the buried layer in the same location.
Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chetlur et al (US 20220115316), Or-Bach et al (US 20230268321) and in further view of Hemmenway et al (US 5920108).
Chetlur et al as modified teaches all of the limitations of the parent claim, claim 3, but does not specifically disclose
[claim 4] The semiconductor structure in claim 3, wherein the first buried insulator layer comprises a thermal oxide layer and a deposited dielectric layer, and a bottom surface of the semiconductor island is fully isolated by first buried insulator layer.
[claim 5] The semiconductor structure in claim 4, further comprising a vertically extended dielectric layer surrounding sidewalls of the semiconductor island.
However, Hemmenway et al does teach
[claim 4] The semiconductor structure in claim 3, wherein the first buried insulator layer comprises a thermal oxide layer and a deposited dielectric layer, and a bottom surface of the semiconductor island is fully isolated by first buried insulator layer (figure 13, col 6 line 36 – col 7 line 10, where element 12 and element 131 contains the first buried insulator layer and contains a thermal oxide layer [element 131] and dielectric layer [element 12]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Chetlur et al as modified to incorporate the teachings of Hemmenway to make the insulating layer a thermal oxide layer with a dielectric layer to maximize thermal transfer.
Regarding claim 5,
Additionally, Or-Bach et al further teaches
[claim 5] The semiconductor structure in claim 4, further comprising a vertically extended dielectric layer surrounding sidewalls of the semiconductor island (figure 2, paragraph 0065, where element 0220 is the vertically extending dielectric layer surrounding the sidewalls of the semiconductor island [element 0216 between element 0220 in figure 2]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Chetlur et al to incorporate the teachings of Or-Bach et al to extend a dielectric wall around the semiconductor island to isolate the semiconductor island with an insulating material.
Claim(s) 8-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chetlur et al (US 20220115316) in view of Gomez et al (US 20080085591).
Chetlur et al as modified teaches all of the limitations of the parent claim, claim 7, but does not specifically disclose
[claim 8] The semiconductor structure in claim 7, wherein the buried layer is a metal containing layer.
[claim 9] The semiconductor structure in claim 7, wherein the buried layer comprises a first portion extending into the STI region.
[claim 10] The semiconductor structure in claim 9, wherein the STI region comprises an oxide layer positioned under the first portion of the buried layer.
[claim 11] The semiconductor structure in claim 10, wherein the STI region comprises a dielectric layer positioned above the first portion of the buried layer.
However, Gomez et al does teach
[claim 8] The semiconductor structure in claim 7, wherein the buried layer is a metal containing layer (figure 4, paragraph 0033, where element 450 is the first buried layer under the semiconductor island [element 472] and contains metal).
[claim 9] The semiconductor structure in claim 7, wherein the buried layer comprises a first portion extending into the STI region (figure 4, paragraph 0033, where element 450 is the first buried layer and has a first portion extending upward from the top surface of the horizontal bottom portion of element 450).
[claim 10] The semiconductor structure in claim 9, wherein the STI region comprises an oxide layer positioned under the first portion of the buried layer (figure 4, paragraph 0033, where element 438 is the STI region [in place of the STI region of Chetlur et al] and has a portion that is in the same plane as the bottom surface of the first buried layer [element 450] which is under the first portion of the buried layer [section of element 450 that extends upward from a top surface of the bottom/horizontal portion of element 450]).
[claim 11] The semiconductor structure in claim 10, wherein the STI region comprises a dielectric layer positioned above the first portion of the buried layer (figure 4, paragraph 0033, where element 438 is the dielectric layer of the STI region that has a portion situated above the top surface of the vertical portion of element 450 [first buried layer] which is above the first portion of the buried layer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Chetlur et al to incorporate the teachings of Gomez et al to incorporate a buried metal layer with dielectric portions isolating the metal layer to isolate the conductive material from other conductive materials through a dielectric layer.
Regarding claims 12-15,
Chetlur et al teaches
[claim 12] A semiconductor structure, comprising: a semiconductor substrate with an original surface (figure 2A, paragraph 0042, where element 202 is the substrate with an original surface [note: original here is defined as inherent to the substrate and not added later, thus a formed substrate has original surfaces]);
a semiconductor island formed based on the semiconductor substrate (figure 2A, paragraph 0042, where element 216A is the semiconductor island formed on the semiconductor substrate [note: “on” has a broad meaning, including have layers between the reference and origin);
a shallow trench isolation (STI) region surrounding the semiconductor island (figure 2A, paragraph 0042, where element 214A is the shallow trench isolation region and surrounds the semiconductor island [element 216A], note that element 214A is an isolation region which surrounds the silicon island [element 216A] and functions similarly to a shallow trench isolation region);
However, Chetlur et al does not specifically disclose
[claim 12] and a buried layer within the STI region and under the original surface of the semiconductor substrate, wherein the buried layer is distributed along a circumference of the semiconductor island, and a thermal conductivity of the buried layer is higher than that of the semiconductor substrate.
[claim 13] The semiconductor structure in claim 12, wherein a top surface of the buried layer is lower than a bottom of the semiconductor island.
[claim 14] The semiconductor structure in claim 12, wherein the buried layer comprises a first portion right under the semiconductor island.
[claim 15] The semiconductor structure in claim 14, wherein a localized insulator layer under the semiconductor island and above the buried layer.
However, Gomez et al does teach
[claim 12] and a buried layer within the STI region and under the original surface of the semiconductor substrate (figure 4, paragraph 0033, where element 450 is the first buried layer and sits under an original surface of the semiconductor substrate [the original surface is defined as the top surface of element 410]),
wherein the buried layer is distributed along a circumference of the semiconductor island, and a thermal conductivity of the buried layer is higher than that of the semiconductor substrate (figure 4, paragraph 0033, where element 472 is the silicon island and the buried layer is distributed along a circumference [outside edges] of the island, and the buried layer is made of metal which is known to have a higher thermal conductivity than the substrate).
[claim 13] The semiconductor structure in claim 12, wherein a top surface of the buried layer is lower than a bottom of the semiconductor island (figure 4, paragraph 0033, where the top surface of element 450 [first buried layer] is below the top surface of the semiconductor island [element 472]).
[claim 14] The semiconductor structure in claim 12, wherein the buried layer comprises a first portion right under the semiconductor island (figure 4, paragraph 0033, where element 450 [first buried layer] has a first portion directly underneath the semiconductor island [element 472]).
[claim 15] The semiconductor structure in claim 14, wherein a localized insulator layer under the semiconductor island and above the buried layer (figure 4, paragraph 0033, where element 438 is the localized insulator layer and has a portion under [below in the vertical direction] the semiconductor island [element 472] and above the buried layer [element 438 extends above element 450]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Chetlur et al to incorporate the teachings of Gomez et al to use a buried layer with high thermal conductivity to maximize heat dissipation from the semiconductor device while insulating it electrically with dielectric layers.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chang et al (US 20160020138), Harper et al (US 9209091), and Howard et al (US 20050012111) as other semiconductor assemblies with a semiconductor island and buried layers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached at 572-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANDREW JOHN ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights