DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
2. Claims 1 and 5 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al. U.S. Patent Application Publication 2024/0321682 A1 (the ‘682 reference).
The reference discloses in Fig. 10 and related text a semiconductor package structure as claimed.
Referring to claim 1, the ‘682 reference discloses a semiconductor package structure, comprising:
a support structure (511, para [36] (paragraph(s) [0036])) comprising a first surface (lower surface) opposite a second surface (upper surface);
a first integrated circuit (IC) chip (210, para [70]) on the first surface (the lower surface) of the support structure (511);
a capping structure (520/upper 510) on the second surface (the upper surface) of the support structure (511); and
a vapor chamber (510, para [35]) disposed in the support structure (511) and over at least a portion of the first IC chip (210).
Referring to claim 5, the reference further discloses that the vapor chamber (510) comprises a vaporizable working fluid sealed within the vapor chamber (para [34]).
3. Claims 1, 5 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ku et al. U.S. Patent Application Publication 2023/0144244 A1 (the ‘244 reference).
The reference discloses in Figs. 13, 1B and related text a semiconductor package structure as claimed.
Referring to claim 1, the ‘244 reference discloses a semiconductor package structure, comprising:
a support structure (vapor chamber lid 931, Fig. 13, para [84, 94]], which is equivalent to vapor chamber lid 131, Fig. 1B, para [40]) comprising a first surface (lower surface) opposite a second surface (upper surface);
a first integrated circuit (IC) chip (905, para [84]) on the first surface (the lower surface) of the support structure (931);
a capping structure (vapor chamber heat sink 331, para [52, 94]) on the second surface (the upper surface) of the support structure (931); and
a vapor chamber (135, Fig. 1B, para [41]) disposed in the support structure (131) and over at least a portion of the first IC chip (115, Fig. 1A, para [26], 905, Fig. 13).
Referring to claim 5, the reference further discloses that the vapor chamber (135) comprises a vaporizable working fluid sealed within the vapor chamber (para [44]).
Referring to claim 7, the reference further discloses that a height (1 nm to 3 nm) of the capping structure (331, para [52]) overlaps in the negative direction a height (2 nm to 4 nm) of the support structure (131, para [40]), meeting the claim range “a height of the capping structure is less than a height of the support structure”.
4. Claims 1 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Parida et al. U.S. Patent Application Publication 2019/0348345 A1 (the ‘345 reference).
The reference discloses in Fig. 4 and related text a semiconductor package structure as claimed.
Referring to claim 1, the ‘345 reference discloses a semiconductor package structure, comprising:
a support structure (vapor chamber lid 400, para [47, 20] (paragraph(s) [0047], [0020])) comprising a first surface (lower surface) opposite a second surface (upper surface);
a first integrated circuit (IC) chip (402a, para [46]) on the first surface (the lower surface) of the support structure (400);
a capping structure (122, para [31]) on the second surface (the upper surface) of the support structure (400); and
a vapor chamber (defined by plates 310/408 (~310/408), para [42, 47] of vapor chamber lid 400, para [42]) disposed in the support structure (400) and over at least a portion of the first IC chip (402a).
Referring to claim 5, the reference further discloses that the vapor chamber (~310/408) comprises a vaporizable working fluid (314, para [42]) sealed within the vapor chamber.
5. Claims 1 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mok et al. U.S. Patent Application Publication 2005/0280128 A1 (the ‘128 reference).
The reference discloses in Fig. 6 and related text a semiconductor package structure as claimed.
Referring to claim 1, the ‘128 reference discloses a semiconductor package structure, comprising:
a support structure (thermal interposer 602, para [67]) comprising a first surface (lower surface) opposite a second surface (upper surface);
a first integrated circuit (IC) chip (608, para [67]) on the first surface (the lower surface) of the support structure (602);
a capping structure (heat sink 110, para [48]) on the second surface (the upper surface) of the support structure (602); and
a vapor chamber (defined by plates 604/606 (~604/606), para [67]) disposed in the support structure (602) and over at least a portion of the first IC chip (608).
Referring to claim 5, the reference further discloses that the vapor chamber (~604/606) comprises a vaporizable working fluid (para [67]) sealed within the vapor chamber.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. §103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 6, 16 and 19-20 are rejected under 35 U.S.C. §103 as being unpatentable over Parida et al. U.S. Patent Application Publication 2019/0348345 A1 (the ‘345 reference) in view of Mok et al. U.S. Patent Application Publication 20050280128.
Referring to claims 6, 16 and 20, the ‘345 reference discloses in Fig. 4 the support structure (400) as detailed above for claim 1 and further discloses (claim 6) that the support structure comprises one or more substrates (408, para [47]) and one or more dielectric layers (310 and/or 105, para [30, 42]), and discloses (claim 16) “a method of forming a semiconductor package structure, comprising: disposing a plurality of integrated circuit (IC) chips (402a,b,c, para [46]) on an interposer structure (substrate 104, para [para [27]); forming a vapor chamber (~312, para [42]) within a support structure (400); bonding the support structure (400) to the plurality of IC chips (400), wherein the vapor chamber (~312) overlies at least a portion of an individual IC chip in the plurality of IC chips (402a,b,c); and bonding a capping structure (122, para [31]) to the support structure”, but does not discloses (claim 6) that the capping structure has a thermal conductivity greater than that of the one or more substrates (of the support structure) and the one or more dielectric layers (of the support structure) and that (claim 16) a thermal conductivity of the capping structure is greater than a thermal conductivity of the support structure .
Mok, in disclosing a semiconductor package as detailed above in paragraph numbered 5, teaches that the vapor chamber (~604/606, para [67]) is formed of silicon for facilitating bonding (attaching) the vapor chamber to the IC chip (608, para [67]) (para [42]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the reference’s vapor chamber (~310/408) utilizing silicon. One would have been motivated to make such a modification in view of the teachings in Mok for facilitating bonding the vapor chamber (~310/408) to the IC chip (402a,b,c).
Thus, such a modification would have resulted in a semiconductor package structure and a method of forming a semiconductor package structure wherein, referring to claim 6, the capping structure (122, formed of copper, para [31]) would have had a thermal conductivity greater than that of the one or more substrates (of the support structure 400) and the one or more dielectric layers (of the support structure 400) (would have been formed of silicon, as taught by Mok), referring to claim 16, wherein a thermal conductivity of the capping structure(122) would have been greater than a thermal conductivity of the support structure (400) (see, for example, Zoorob et al. U.S. Patent Application Publication 20110133224, Table 1, disclosing that copper has a thermal conductivity of 400 W/m K and silicon has a thermal conductivity of 150 W/m K), and referring to claim 20, wherein the support structure (400) comprises a substrate (408), wherein the substrate (408) would have comprised silicon (as taught by Mok) and the capping structure (122) comprises copper (para [31]).
Referring to claim 19, the ‘345 reference further discloses forming a thermal dispersion enhancement structure along at least one surface of the one or more surfaces of the support structure (400) defining the vapor chamber (~310/408), wherein the thermal dispersion enhancement structure comprises a wicking layer (332, para [42]).
Allowable Subject Matter
7. Claims 9-15 are allowable over the prior art of record.
Claims 2-4, 8 and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to teach or render obvious a semiconductor package structure and a method of forming a semiconductor package structure with all exclusive limitations as recited in claims 2, 8, 9, and 17, which may be characterized (claim 2) in that the vapor chamber comprises a first chamber portion and a second chamber portion overlying the first chamber portion, and in that a width of the first chamber portion is less than a width of the second chamber portion, (claim 9) the one or more vapor chambers respectively comprise a bottom surface with a first width facing the plurality of IC chips and a top surface with a second width facing the heat spreader structure, and in that the first width is less than the second width, (claim 17) in etching a first substrate to define a first chamber portion in the first substrate, etching a second substrate to define a second chamber portion in the second substrate, and in that a width of the second chamber portion is greater than a width of the first chamber portion, and (claim 8) a thermal interface structure disposed between the capping structure and the support structure, in that the thermal interface structure comprises a first thermal spreading layer, a second thermal spreading layer, and a thermal interface layer between the first and second thermal spreading layers, and in that the first and second thermal spreading layers comprise a first material different from a second material of the thermal interface layer.
Conclusion
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TU TU V HO whose telephone number is (571)272-1778. The examiner can normally be reached on Monday to Thursday 6:30 - 15:00, Monday through Thursday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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07-28-2026
/TU-TU V HO/Primary Examiner, Art Unit 2818
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