DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1, 13 and 19 are objected to because of the following informalities:
For example, claim 1 recites the limitation “said mold” in line 5 and “the mold” in line 9.
Applicants use both “the” and “said” throughout the claims in order to establish proper antecedent basis. However, such usage confuses the claim language. Applicant(s) is/are advised to use either “the” or “said” consistently throughout the claim language. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12, recites the limitation wherein the active semiconductor layer comprises at least one of indium gallium zinc oxide (InxGayZnzO), indium tungsten oxide (InxWyO), indium tin gallium oxide (InxSnyGazO), indium aluminum zinc oxide (InxAlyZnzO), indium gallium oxide (InxGayO), indium tin zinc oxide (InxSnyZnzO), indium gallium silicon oxide (InxGaySizO), indium zinc oxide (InxZnyO), indium oxide (InxO), magnesium aluminum zinc oxide (MgxAlyZnzO), zinc tin oxide (ZnxSnyO), zirconium zinc tin oxide, (ZrxZnySnzO), gallium zinc tin oxide (GaxZnySnzO), aluminum zinc tin oxide (AlxZnySnzO), and tin oxide (SnxO)” in lines 2-8.
Since the meets and bounds of x, y and z is not defined in the claim, the underlined limitations for the metal oxide layers renders the claim indefinite because the scope of x, y and z is not known.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by KIM (US 2023/0413524).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
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Re Claim 1, KIM discloses a semiconductor device, comprising: a bit line (120 Fig. 3) extending in a first horizontal direction across an underlying substrate (110); a mold structure (130, Paragraph [0036]), which extends on the bit line (120) and has a mold opening (130H, Paragraph [0036[) therein that extends in a second horizontal direction perpendicular to the first horizontal direction, said mold structure (130) including a mold insulating layer (130), a cover insulating layer (172) extending on the mold insulating layer (see Fig. 3), and an interface insulating layer (176) extending on an upper surface of and on at least a portion of a sidewall of the cover insulating layer (Fig. 3); an active semiconductor layer (140) including: a first portion extending on an inner wall of the mold opening in the mold structure, and in a vertical direction perpendicular to an upper surface of the substrate (i.e., the channel layer 140 having U shape), said first portion having a first sidewall in contact with a sidewall of the mold opening and a second sidewall extending opposite the first sidewall; and a second portion connected to the bottom of the first portion and extending in the first horizontal direction and on an upper surface of the bit line (see Fig. 3); a word line (170) extending on the second sidewall of the active semiconductor layer and in the second horizontal direction; and a gate insulating layer (150) extending between the active semiconductor layer and the word line (see Fig. 3 and related text in Paragraphs [0034] – [0052]).
Re Claim 2, as applied to claim 1 above, KIM discloses all the claimed limitations including a landing pad (180) extending on an upper surface of the first portion of the active semiconductor layer (140); wherein the interface insulating layer (180) extends between the landing pad and the cover insulating layer (174); and wherein the landing pad is not in contact with the cover insulating layer (Fig. 3).
Re Claim 3, as applied to claim 1 above, KIM discloses all the claimed limitations including wherein the active semiconductor layer has a U-shaped vertical cross-section; and wherein the word line has an L-shaped vertical cross-section (see Fig. 3 and related text in Paragraphs [0034] – [0052]).
Re Claim 4, as applied to claim 1 above, KIM discloses all the claimed limitations including a landing pad extending on an upper surface of the first portion of the active semiconductor layer; wherein the landing pad includes an upper portion and a bottom portion; wherein the bottom portion of the landing pad extends in a landing pad recess space defined between the mold structure and the gate insulating layer on an upper surface of the active semiconductor layer; and wherein the upper portion of the landing pad is disposed on an upper surface of the mold structure (see Fig. 3 and related text in Paragraphs [0034] – [0052]).
Re Claim 5, as applied to claim 4 above, KIM discloses all the claimed limitations including wherein the upper portion of the landing pad has a first width in the first horizontal direction; wherein the bottom portion of the landing pad has a second width that is less than the first width in the first horizontal direction (see Fig. 3 and related text in Paragraphs [0034] – [0052]).
Re Claim 6, as applied to claim 4 above, KIM discloses all the claimed limitations including wherein the interface insulating layer extends from the upper surface of the cover insulating layer onto the sidewall of the cover insulating layer extending in the landing pad recess space; and wherein a portion of the interface insulating layer extending on the sidewall of the cover insulating layer is in contact with the landing pad (see Fig. 3 and related text in Paragraphs [0034] – [0052]).
Re Claim 7, as applied to claim 6 above, KIM discloses all the claimed limitations including wherein the first portion of the active semiconductor layer has an upper surface disposed at a same or lower level than a bottom surface of the cover insulating layer; and wherein the entire sidewall of the cover insulating layer extending in the landing pad recess space is covered by the interface insulating layer (see Fig. 3 and related text in Paragraphs [0034] – [0052]).
Re Claim 8, as applied to claim 6 above, KIM discloses all the claimed limitations including wherein the first portion of the active semiconductor layer has an upper surface disposed at a higher level than a bottom surface of the cover insulating layer; wherein an upper side of the sidewall of the cover insulating layer extending in the landing pad recess space is covered by the interface insulating layer; and wherein a lower side of the sidewall of the cover insulating layer is in contact with a sidewall of the first portion of the active semiconductor layer (see Fig. 3 and related text in Paragraphs [0034] – [0052]).
Re Claim 9, as applied to claim 4 above, KIM discloses all the claimed limitations including a buried insulating (174) layer extending on a sidewall of the word line and filling the mold opening; and wherein a portion of a bottom surface of the upper portion of the landing pad is disposed on an upper surface of the buried insulating layer (see Fig. 3 and related text in Paragraphs [0034] – [0052]).
Re Claim 10, as applied to claim 1 above, KIM discloses all the claimed limitations including wherein a bottom surface of the landing pad is disposed at a same level as a bottom surface of the interface insulating layer (see Fig. 3 and related text in Paragraphs [0034] – [0052]).
Re Claim 11, as applied to claim 1 above, KIM discloses all the claimed limitations including wherein the interface insulating layer includes at least one of silicon oxynitride and silicon oxide (see Fig. 3 and related text in Paragraphs [0034] – [0052]).
Re Claim 12, as applied to claim 1 above, KIM discloses all the claimed limitations including wherein the active semiconductor layer comprises at least one of indium gallium zinc oxide (InxGayZnzO), indium tungsten oxide (InxWyO), indium tin gallium oxide (InxSnyGazO), indium aluminum zinc oxide (InxAlyZnzO), indium gallium oxide (InxGayO), indium tin zinc oxide (InxSnyZnzO), indium gallium silicon oxide (InxGaySizO), indium zinc oxide (InxZnyO), indium oxide (InxO), magnesium aluminum zinc oxide (MgxAlyZnzO), zinc tin oxide (ZnxSnyO), zirconium zinc tin oxide, (ZrxZnySnzO), gallium zinc tin oxide (GaxZnySnzO), aluminum zinc tin oxide (AlxZnySnzO), and tin oxide (SnxO). See Paragraph [0039].
Re Claim 13, KIM discloses a semiconductor device, comprising: a bit line (120) extending in a first direction, on an underlying substrate (110); a mold structure (130) having a mold opening (130H) therein that extends in a second direction, which is perpendicular to the first direction, said mold structure (130) extending on the bit line and comprising a mold insulating layer, a cover insulating layer on the mold insulating layer, and an interface insulating layer on an upper surface of and on at least a portion of a sidewall of the cover insulating layer; an active semiconductor layer including a first portion extending on an inner wall of the mold opening in the mold structure and extending in a vertical direction perpendicular to an upper surface of the substrate, and a second portion, which is connected to the bottom of the first portion and extends in the first direction; a word line (170) extending on the second sidewall of the active semiconductor layer and extending in the second horizontal direction; a gate insulating (150) layer extending between the active semiconductor layer and the word line; and a landing pad (180) electrically connected to an upper surface of the first portion of the active semiconductor layer (140), said landing pad comprising an upper portion extending on an upper surface of the mold structure and a bottom portion connected to the upper portion and extending in a landing pad recess space; wherein a bottom surface of the bottom portion of the landing pad extends at a same level as a bottom surface of the interface insulating layer; wherein the first portion includes a first sidewall in contact with a sidewall of the mold opening and a second sidewall extending opposite to the first sidewall; and wherein the second portion extends on an upper surface of the bit line (see Fig. 3 and related text in Paragraphs [0034] – [0052]).
Re Claim 14, as applied to claim 13 above, KIM discloses all the claimed limitations including wherein the interface insulating layer extends from the upper surface of the cover insulating layer onto a sidewall of the cover insulating layer disposed in the landing pad recess space; and wherein a portion of the interface insulating layer disposed on the sidewall of the cover insulating layer is in contact with the bottom portion of the landing pad (see Fig. 3 and related text in Paragraphs [0034] – [0052]).
Re Claim 15, as applied to claim 14 above, KIM discloses all the claimed limitations including wherein the interface insulating layer extends between the bottom portion of the landing pad and the cover insulating layer; and wherein the bottom portion of the landing pad is not in contact with the cover insulating layer (see Fig. 3 and related text in Paragraphs [0034] – [0052]).
Re Claim 16, as applied to claim 13 above, KIM discloses all the claimed limitations including wherein the first portion of the active semiconductor layer has an upper surface disposed at a same or lower level than the bottom surface of the cover insulating layer; and wherein an entire sidewall of the cover insulating layer disposed in the landing pad recess space is covered by the interface insulating layer (see Fig. 3 and related text in Paragraphs [0034] – [0052]).
Re Claim 17, as applied to claim 13 above, KIM discloses all the claimed limitations including a buried insulating layer extending on a sidewall of the word line and filling the mold opening; and wherein a portion of a bottom surface of the upper portion of the landing pad extends on an upper surface of the buried insulating layer (see Fig. 3 and related text in Paragraphs [0034] – [0052]).
Re Claim 18, as applied to claim 13 above, KIM discloses all the claimed limitations including wherein the interface insulating layer includes silicon oxynitride or silicon oxide, and the cover insulating layer includes silicon nitride (see Fig. 3 and related text in Paragraphs [0034] – [0052]).
Re Claim 19, KIM discloses a semiconductor device, comprising: a bit line (120) extending in a first horizontal direction on a substrate; a mold structure extending on the bit line and having a mold opening therein, which extends in a second direction perpendicular to the first horizontal direction, said mold structure comprising a mold insulating layer (130), a cover insulating layer (172) disposed on the mold insulating layer (130), and an interface insulating layer disposed on an upper surface of and on at least a portion of a sidewall of the cover insulating layer; an active semiconductor layer including a first portion disposed on an inner wall of the mold opening (130H) of the mold structure and extending in a vertical direction perpendicular to an upper surface of the substrate, and a second portion connected to the bottom of the first portion and extending in the first horizontal direction, wherein the second portion extends on an upper surface of the bit line, and the first portion includes a first sidewall in contact with a sidewall of the mold opening and a second sidewall opposite to the first sidewall, and wherein the active semiconductor layer (140) has an upper surface extending at a lower level than an upper surface of the mold structure; a word line extend on the second sidewall of the active semiconductor layer and extending in the second horizontal direction; a gate insulating layer disposed between the active semiconductor layer and the word line; a buried insulating layer (174) extending on a sidewall of the word line and filling the mold opening (130H); a landing pad electrically connected to an upper surface of the first portion of the active semiconductor layer, said landing pad including an upper portion disposed on the upper surface of the mold structure and a bottom portion connected to the upper portion and disposed in a landing pad recess space; and a storage node connected to the landing pad; wherein the interface insulating layer extends from the upper surface of the cover insulating layer onto a sidewall of the cover insulating layer extending in the landing pad recess space (see Fig. 3 and related text in Paragraphs [0034] – [0052]).
Re Claim 20, (Original) The semiconductor device of claim 19, wherein the first portion of the active semiconductor layer has an upper surface disposed at a same or lower level than a bottom surface of the cover insulating layer; wherein an entire sidewall of the cover insulating layer disposed in the landing pad recess space is covered by the interface insulating layer; and wherein the interface insulating layer extends between the bottom portion of the landing pad and the cover insulating layer and is not in contact with the cover insulating layer (see Fig. 3 and related text in Paragraphs [0034] – [0052]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure KIM (US 2023/0292492) disclose similar inventive subject matter that includes bit-line over a substrate and mold layer, active layer embedded word-line and embedded insulating layer, KIM reference is also a potential 102(a)(2) reference.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BROOK KEBEDE whose telephone number is 571-272-1862. The examiner can normally be reached Monday Friday 8:00 AM 5:00 PM.
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/BROOK KEBEDE/
Primary Examiner, Art Unit 2894
/BK/
June 26, 2026
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