Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 10 and 11 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Lilak (US 20190196830 A1).
Regarding claim 1, Lilak discloses a method of forming an integrated circuit device, the method comprising: forming a preliminary stacked structure (Figs. 2A-8B) that comprises: first and second lower source/drain regions (left and right instances of 118-1 respectively) on a substrate (102)and spaced apart from each other in a first horizontal direction (X direction, parallel to page in B figures) that is parallel to an upper surface of the substrate (Shown); a lower active region (106-1) between the first and second lower source/drain regions and contacting the first and second lower source/drain regions (Shown); first and second upper source/drain regions (left and right instances of 118-2 respectively) on the first and second lower source/drain regions and spaced apart from each other in the first horizontal direction (Shown); an upper active region (106-2) between the first and second upper source/drain regions and contacting the first and second upper source/drain regions (Shown); a sacrificial gate structure (104) on the lower and upper active regions (Shown best in Fig. 8A), between the first and second lower source/drain regions, and between the first and second upper source/drain regions (Fig. 8B shows 104 between upper and lower S/D regions); and an insulating layer (comprises 110 and 112; para. 33 "The dummy gate dielectric 110 and the dummy gate metal 112 may include any suitable materials… silicon oxide", where silicon oxide is a well-known insulator) on the substrate (Shown), wherein the first and second lower source/drain regions and the first and second upper source/drain regions are in the insulating layer (Shown best in Fig.8B); and replacing the sacrificial gate structure with a lower gate structure (Shown in Fig. 14B, 124-1) and an upper gate structure (124-2), wherein the lower gate structure is on the lower active region and between the first and second lower source/drain regions (Shown), and the upper gate structure is on the upper active region and between the first and second upper source/drain regions (Shown), wherein the lower gate structure has a first width in the first horizontal direction (width of 124-1 in Fig. 14B), and the upper gate structure has a second width in the first horizontal direction (width of 124-2 in Fig. 14B), the lower gate structure has a third width (width of 124-1 in Fig. 14A) in a second horizontal direction (Y direction, going into page in B figures) that is perpendicular to the first horizontal direction (Para. 20 "Each device stratum 130 may include channel material 106 having a longitudinal axis (into the page from the perspective of FIG. 1A and left right from the perspective of FIG. 1B)", which would imply that A and B figures are perpendicular cross sections of each other) and is parallel to the upper surface of the substrate (Both X and Y directions are necessarily parallel to upper surface of the substrate), and the upper gate structure has a fourth width in the second horizontal direction (width of 124-2 in Fig. 14A), and the first width is different from the second width, or the third width is different from the fourth width (Fig. 14B shows 124-1 and 124-2 having different widths).
Regarding claim 10, Lilak further discloses wherein the upper gate structure comprises an upper gate electrode (Fig. 14B, 124-2) on the upper active region (Shown), and the lower gate structure comprises a lower gate electrode (124-1) on the lower active region (Shown), and the upper gate electrode comprises a material different from the lower gate electrode (Para. 24 "the material composition of the gate metal 124 used in different ones of the device strata 130 may be different; for example, FIG. 1 illustrates a gate metal 124-1 in the device stratum 130-1 and a gate metal 124-2 in the device stratum 130-2").
Regarding claim 11, Lilak further discloses wherein the first and second upper source/drain regions have a conductivity type different from a conductivity type of the first and second lower source/drain regions (Para. 45 "when the transistors of the device strata 130-1 in the dashed box are PMOS transistors, and the transistors of the device strata 130-2 in the dashed box are NMOS transistors", which would necessitate different conductivity types for different source/drain regions in 130-1 and 130-2).
Allowable Subject Matter
Claims 2-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, the prior art of record fails to disclose the method of claim 1, wherein replacing the sacrificial gate structure with the lower gate structure and the upper gate structure comprises: forming an opening in the insulating layer by removing the sacrificial gate structure, wherein the opening is between the first and second lower source/drain regions and is between the first and second upper source/drain regions; forming a first spacer layer on sides of the opening; forming a second spacer layer on a lower portion of the first spacer layer, wherein the second spacer layer defines a lower opening, and an upper portion of the first spacer layer defines an upper opening; forming the lower gate structure in the lower opening; and forming the upper gate structure on the lower gate structure in the upper opening. Specifically, the prior art of record fails to disclose a first spacer layer formed on sides of the opening.
For this reason, claims 3-5 would also be allowable if claim 2 were rewritten in independent form.
Regarding claim 6, the prior art of record fails to disclose the method of claim 1, wherein replacing the sacrificial gate structure with the lower gate structure and the upper gate structure comprises: forming an opening in the insulating layer by removing the sacrificial gate structure, wherein the opening is between the first and second lower source/drain regions and between the first and second upper source/drain regions; forming a first spacer layer on sides of the opening; forming the lower gate structure in a lower portion of the opening; forming a second spacer layer on the first spacer layer and on the lower gate structure, the second spacer layer defining an upper opening; and forming the upper gate structure in the upper opening. Specifically, the prior art of record fails to disclose forming a second spacer layer on the first spacer layer and on the lower gate structure.
For this reason, claims 7-9 would also be allowable if claim 6 were rewritten in independent form.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL J SMITH whose telephone number is (703)756-5706. The examiner can normally be reached M-F 8-5 EST.
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/S.J.S./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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