DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Claim Objections 3
III. Claim Rejections - 35 USC § 103 3
A. Claims 1-4 and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0342453 (“Ziglioli”). 4
IV. Allowable Subject Matter 8
V. Pertinent Prior Art 10
Conclusion 11
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Claim Objections
Claims 11 and 20 are objected to because of the following informalities:
In claim 11, line 11, replace “onr” with “on” to correct typographical error.
In claim 20, line 1, replace “method” with “device” for clarity.
Appropriate correction is required.
III. Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 1-4 and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0342453 (“Ziglioli”).
Claim 11 reads,
11. A device, comprising:
[1a] a substrate having electrically conductive substrate portions, wherein
[1b] the electrically conductive substrate portions comprise a die mounting location and
[1c] a plurality of electrically conductive leads around the die mounting location;
[2] a semiconductor die mounted on a first surface of the die mounting location of the substrate;
[3a] a first electrically insulating encapsulation which encapsulates both the substrate and the semiconductor die,
[3b] wherein the first electrically insulating encapsulation has a surface opposite the first surface of the die mounting location;
[4] an opening in the first electrically insulating encapsulation exposing a die bonding pad of the semiconductor die;
[5] an electrically conductive path section extending through and onr the first electrically insulating encapsulation between an electrically conductive lead and an intermediate point at the surface of the first electrically insulating encapsulation; and
[6] a wire bonding in said opening in the first electrically insulating encapsulation and extending between the die bonding pad of the semiconductor die and the electrically conductive path section at said intermediate point.
With regard to claim 11, Ziglioli discloses, generally in Figs. 3, 7, 9, and 10,
11. A device, comprising:
[1a] a substrate [lead frame 10] having electrically conductive substrate portions 12, 14 [¶¶ 57-58], wherein
[1b] the electrically conductive substrate portions 12, 14 comprise a die mounting location [die pad 12] and
[1c] a plurality of electrically conductive leads [leads 14] around the die mounting location 12;
[2] a semiconductor die 22 [¶ 76] mounted on a first surface of the die mounting location 12 of the substrate 10;
[3a] a first electrically insulating encapsulation 20 which encapsulates both the substrate 10 and …,
[3b] wherein the first electrically insulating encapsulation 20 has a surface opposite the first surface of the die mounting location 12;
[4] an opening in the first electrically insulating encapsulation 20 exposing a die bonding pad of the semiconductor die 22 [bonding pads are not shown but are the location where the wire bonds 24 are contacting the active surface of the die 22, as explained in ¶ 76];
[5] an electrically conductive path section 18 extending through and onr [sic] the first electrically insulating encapsulation 20 [as shown in Fig. 3 (¶¶ 49-50, 63-66)] between an electrically conductive lead 14 and an intermediate point [pad portion where wire 24 contacts trace 18] at the surface of the first electrically insulating encapsulation 20 [as shown in Fig. 7]; and
[6] a wire bonding 24 in said opening in the first electrically insulating encapsulation 20 and extending between the die bonding pad of the semiconductor die 22 and the electrically conductive path section 18 at said intermediate point [as shown in Fig. 7].
With regard to feature [3a] of claim 1, the embodiment shown in Fig. 7 does not show that the semiconductor device 22 is encapsulated in the first encapsulant 20.
However, the embodiments shown in Fig. 14 includes the limitation in feature [3a] requiring the semiconductor die 22 to be encapsulated in the first encapsulation 20, on which the electrically conductive path, i.e. trace 18, is formed.
Ziglioli further states that the embodiment shown in Figs. 14-16 may be combined with embodiments in other figures:
[0083] FIGS. 14 to 16 are exemplary of further possible variants in one or more embodiments.
[0084] It will be again noted that features exemplified in connection with embodiments exemplified in any one of the figures can be applied, individually or in combination, also to embodiments exemplified in any other of the figures.
(Ziglioli: ¶¶ 83-84; emphasis added)
Thus, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the embodiment shown in Fig. 7 with any of the embodiments shown in Figs. 14-16 because Ziglioli explicitly suggests that any of the embodiments in any of the figures can be combined.
In making the combination, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to encapsulate the semiconductor die 22 in the first encapsulation 20 along with the lead frame and, then, form the traces 18 to extend on and through the surface of the first encapsulation 20 to a point short of the die pads (as shown in Figs. 3 and 4), and then to connect the traces 18 to the bonding pads of the die 22 using the wire bonds 24, as shown in Fig. 7, as this provides the combination of the embodiments in Fig. 7 with the embodiments in Figs. 14-16.
This is all of the limitations of claim 11.
With regard to claim 12, Ziglioli further discloses,
12. The device of claim 11, further comprising a second electrically insulating encapsulation 20' which encapsulates the electrically conductive path section 18 and the wire bonding 24 [¶ 87; as shown in Fig. 16].
Claim 12 is the addition of the second encapsulation 20' on the embodiment that is the combination of Fig. 7 with the embodiment in Figs. 14-16.
With regard to claims 13 and 14, Ziglioli further discloses,
13. The device of claim 11, wherein the die mounting location 12 has a downset with respect to the plurality of electrically conductive leads 12 around the die mounting location [¶ 58: “the die pad 12 is “downset” with respect to the leads 14”].
14. The device of claim 11, wherein the first electrically insulating encapsulation 20 comprises a laser direct structuring (LDS) molding compound [¶¶ 49-50, 63-66].
With regard to claim 1, the combination of the embodiments shown in Fig. 7 with Figs. 14-16 of Ziglioli, as explained under claim 11, above, further teaches,
1. A method [Fig. 1], comprising:
[1a] mounting a semiconductor die 22 on a substrate 10 having electrically conductive substrate portions 12, 14,
[1b] wherein the electrically conductive substrate 10 portions comprise a die mounting location 12 and a plurality of electrically conductive leads 14 around the die mounting location 12,
[1c] wherein the semiconductor die 22 is mounted on a first surface of the die mounting location 12;
[2] encapsulating both the semiconductor die 22 and the substrate 10 in a first electrically insulating encapsulation 20 [as shown in Figs. 14-16], wherein the first electrically insulating encapsulation 20 has a surface opposite the first surface of the die mounting location 12;
[3] providing an opening in the surface of the first electrically insulating encapsulation to expose a die bonding pad [pads where wire bonds 24 will be formed, as shown in Figs. 7 and 15] of the semiconductor die 22 [as shown in Figs. 14 and 15];
[4] providing an electrically conductive path section 18 extending through and on the first electrically insulating encapsulation 20 between an electrically conductive lead 14 and an intermediate point at the surface of the first electrically insulating encapsulation 20 [as shown in Figs. 3 and 7 (¶¶ 49-50, 63-66)];
[5] providing a wire bonding 24 in said opening in the surface of the first electrically insulating encapsulation 20 and extending between the die bonding pad of the semiconductor die 22 and the electrically conductive path section 18 at said intermediate point [as shown in Fig. 7].
With regard to claims 2-4, Ziglioli further discloses,
2. The method of claim 1, further comprising encapsulating the electrically conductive path section 18 and the wire bonding 24 in a second electrically insulating encapsulation 20' [as shown in Fig. 16].
3. The method of claim 1, wherein the die mounting location 12 has a downset with respect to the plurality of electrically conductive leads 14 around the die mounting location 12 [as shown in Figs. 3, 7, and 14-16].
4. The method of claim 1, wherein the first electrically insulating encapsulation 20 comprises a laser direct structuring (LDS) molding compound [¶¶ 49-50, 63-66].
IV. Allowable Subject Matter
Claims 5-10 and 15-20, pending overcoming the objection of claim 20, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 5 and 15 read,
5. The method of claim 4, wherein providing the electrically conductive path section comprises:
[1] LDS processing said LDS molding compound to form a trace and a via opening; and
[2] forming electrically conductive structures at said trace and via opening.
15. The device of claim 14, wherein the electrically conductive path section comprises:
[1] a trace and a via opening formed by LDS processing in said LDS molding compound; and
[2] electrically conductive structures at said trace and via opening.
As explained under claims 11 and 14, Ziglioli uses LDS processing in the LDS encapsulation material 20 to form the traces and electrically conductive patterns 18 filling the traces (¶¶ 49-50, 63-66). Ziglioli does not disclose the via opening because no via opening is required, and it is not clear that one having ordinary skill in the art would modify the encapsulation layer 20 to cover the entire active surface of the die and the leads 14 with said encapsulation 20 in order to necessitate the formation of the via openings exposing each of the bonding pads of the die 22 and the leads 14.
The prior art does not reasonably teach or suggest—in the context of claim 5—the limitation, “… a via opening formed by LDS processing in said LDS molding compound”.
Although the “LDS processing” recited in claim 15 fails to have patentable weight for being a product-by-process limitation, Ziglioli still fails to disclose the claimed “via opening”.
Claim 16 reads,
16. The device of claim 11, further comprising:
[1] a further opening in the first electrically insulating encapsulation exposing a further die bonding pad of the semiconductor die;
[2] a further electrically conductive path section extending through and/or over the first electrically insulating encapsulation between the substrate and a further intermediate point at the surface of the first electrically insulating encapsulation; and
[3] a further wire bonding in said further opening and extending between the further die bonding pad of the semiconductor die and the further electrically conductive path section at said further intermediate point.
Fig. 7 shows that there are plural wire bonds 24 connected plural traces 18 to plural bonding pads on the semiconductor die, as required by features [2] and [3] of claim1. However, Ziglioli does not disclose separate openings for each of the die bond pads, and it is not clear that one having ordinary skill in the art would include separate openings for each die bond pad, given that the entire active surface of the die 22 is exposed by a single opening in the first encapsulation 20 shown in Figs. 7 and 14-16.
As such, the prior art does not reasonably teach or suggest—in the context of claim 16—the limitation “a further opening in the first electrically insulating encapsulation exposing a further die bonding pad of the semiconductor die”.
Claims 17-20 would be allowable for including the same allowable limitation by depending from claim 16, either directly or indirectly.
Claim 6 reads,
6. The method of claim 1, further comprising:
[1] providing a further opening in the first electrically insulating encapsulation to expose a further die bonding pad of the semiconductor die;
[2] providing a further electrically conductive path section extending through and on the first electrically insulating encapsulation between the substrate and a further intermediate point at the surface of the first electrically insulating encapsulation; and
[3] providing a further wire bonding in said further opening and extending between the further die bonding pad of the semiconductor die and the further electrically conductive path section at said further intermediate point.
Claim 6 includes the same allowable limitations as those recited in claim 16.
Claims 7-10 would be allowable for including the same allowable limitation by depending from claim 6, either directly or indirectly.
V. Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
The following references are cited for including a physically connected trace and bond wire electrically connecting the bond pad of a die to a lead of a lead frame:
US 6,936,495 (“Chiang”): See at least Figs. 3A, 3E, 4A, 4C, 5A, 7D, 9B, and 11A-11E, and the associated text.
US 6,774,659 (“Chiang”): See at least Figs. 3A, 3E, 5A, 7D, and 11A-11E and associated text.
US 5,796,570 (“Mekdhanasarn”): See at least Fig. 2 and associated text.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814
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