DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on November 12, 2025, has been entered.
Claims 1-20 are pending in this office action and presented for examination. Claims 1-20 are newly amended by the response received November 12, 2025.
Examiner notes that an amendment to paragraph 21 of the specification of the response received November 12, 2025, appears to have been previously made in an amendment to the specification of the response received August 20, 2025.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 11, 13, and 17 are rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, because the claim purports to invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, but fails to recite a combination of elements as required by that statutory provision and thus cannot rely on the specification to provide the structure, material or acts to support the claimed function. As such, the claim recites a function that has no limits and covers every conceivable means for achieving the stated function, while the specification discloses at most only those means known to the inventor. Accordingly, the disclosure is not commensurate with the scope of the claim.
Claims 4-5, 7, and 10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 4 recites the limitation “the undefined portion includes one or more of an opcode field, a register identifier field, at least part of a memory address field, an operand field, a coefficient field, and a command buffer index field” in lines 1-4. However, this subject matter was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. For example, an undefined portion (singular) including more than one of “an opcode field, a register identifier field, at least part of a memory address field, an operand field, a coefficient field, and a command buffer index field”, which is a scenario encompassed by the claim language in view of the “one or more” language, does not appear to be described in the specification (e.g., paragraph [0021] and paragraph [0025]) in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 5 recites the limitation “the defined portion includes one or more of an opcode, a register identifier, at least part of a memory address of the memory, an operand, a coefficient, and a command buffer index” in lines 1-4. However, this subject matter was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. For example, a defined portion (singular) including more than one of “an opcode, a register identifier, at least part of a memory address of the memory, an operand, a coefficient, and a command buffer index”, which is a scenario encompassed by the claim language in view of the “one or more” language, does not appear to be described in the specification (e.g., paragraph [0021] and paragraph [0026]) in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 7 recites the limitation “the undefined portion of the conditional instruction includes at least one register identifier field for storing one or more of a reference value used during execution and a result of the execution” in lines 1-4. However, this subject matter was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. For example, an undefined portion (singular) including more than one “register identifier field for storing one or more of a reference value used during execution and a result of the execution”, which is a scenario encompassed by the claim language in view of the “one or more” language, does not appear to be described in the specification (e.g., paragraph [0021] and paragraph [0025]) in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 10 recites the limitation “the undefined portion includes at least one register identifier field, the defined portion includes a plurality of register values corresponding to the at least one register identifier field, and the in-memory processor is further configured to coalesce the plurality of register values during execution of the instruction” in lines 1-7. However, this subject matter was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. For example, the undefined portion (singular) including more than one register identifier field, the defined portion (singular) including a plurality of register values corresponding to the more than one register identifier field, and the in-memory processor is further configured to coalesce the plurality of register values during execution of the instruction, which is a scenario encompassed by the claim language in view of the “one or more” language, does not appear to be described in the specification (e.g., paragraph [0021], paragraph [0025], and paragraph [0026]) in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “an instruction delta that is an undefined portion of an instruction of a processing-in-memory (PIM) command” in lines 4-6. However, instant paragraph [0021] discloses ‘As used herein, the term “instruction deltas” refers to undefined portions of data instructions (e.g., contained in PIM commands) that remain undefined (e.g., in a command buffer) until the data instruction is executed.’ Therefore, the metes and bounds of “instruction delta” are indefinite. For example, the definition that appears to be conveyed via the limitation appears to be different in scope from the definition that appears to be conveyed via paragraph [0021] (after extrapolating the “singular” definition from the “plural” definition). For example, it is unclear as to whether the language associated with “e.g.” in paragraph [0021] is part of the claimed invention.
Claims 2-10 are rejected for failing to alleviate the rejection of claim 1 above.
Claim 11 recites the limitation “an instruction delta that is an undefined portion of an instruction of a processing-in-memory (PIM) command” in lines 4-5. However, instant paragraph [0021] discloses ‘As used herein, the term “instruction deltas” refers to undefined portions of data instructions (e.g., contained in PIM commands) that remain undefined (e.g., in a command buffer) until the data instruction is executed.’ Therefore, the metes and bounds of “instruction delta” are indefinite. For example, the definition that appears to be conveyed via the limitation appears to be different in scope from the definition that appears to be conveyed via paragraph [0021] (after extrapolating the “singular” definition from the “plural” definition). For example, it is unclear as to whether the language associated with “e.g.” in paragraph [0021] is part of the claimed invention.
Claims 12-18 are rejected for failing to alleviate the rejection of claim 11 above.
Claim 18 recites the limitation “the delta decode unit is configured to decode the instruction delta into a single defined portion of the instruction to be used during the execution of the instruction, or the delta decode unit is configured to decode the instruction delta into multiple defined portions of the instruction to be used during the execution of the instruction” in lines 2-6. Claim 11, upon which claim 18 is indirectly dependent, recites the limitation “identify an instruction delta that is an undefined portion of an instruction of a processing-in-memory (PIM) command; decode the instruction delta into a defined portion of the instruction to be used during execution of the instruction in place of the undefined portion” in lines 4-8. However, it is indefinite as to whether “a single defined portion” of claim 18, line 3, is the same as, or different from, “a defined portion” as recited in claim 11, lines 6-7. In addition, the limitation of claim 18 appears to convey one instruction delta being decoded into multiple defined portions; however, paragraphs [0021] and [0024]-[0026] of the instant specification, for example, as well as parent claims 11 and 14 as amended to overcome an analogous indefinite rejection, appear to convey that an instruction delta is decoded into a single defined portion. A claim, although clear on its face, may also be indefinite when a conflict or inconsistency between the claimed subject matter and the specification disclosure renders the scope of the claim uncertain as inconsistency with the specification disclosure or prior art teachings may make an otherwise definite claim take on an unreasonable degree of uncertainty. Therefore, because the aforementioned limitation appears to conflict with the specification in the manner explained above, the claim is indefinite.
Claim 19 recites the limitation “an instruction delta that is an undefined portion of an instruction” in lines 2-3. However, instant paragraph [0021] discloses ‘As used herein, the term “instruction deltas” refers to undefined portions of data instructions (e.g., contained in PIM commands) that remain undefined (e.g., in a command buffer) until the data instruction is executed.’ Therefore, the metes and bounds of “instruction delta” are indefinite. For example, the definition that appears to be conveyed via the limitation appears to be different in scope from the definition that appears to be conveyed via paragraph [0021] (after extrapolating the “singular” definition from the “plural” definition). For example, it is unclear as to whether the language associated with “e.g.” in paragraph [0021] is part of the claimed invention.
Claim 20 is rejected for failing to alleviate the rejection of claim 19 above.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-13, 17, and 19-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. See MPEP 2106.
Regarding Eligibility Step 1, each of the claims is directed to a process, machine, manufacture, or composition of matter.
Regarding Eligibility Step 2A, Prong One, each of the claims recites abstract ideas. Specifically, each of the claims recites mental processes that can be performed in the human mind, or by a human using a pen and paper. For example, independent claim 19 recites identifying an instruction delta that is an undefined portion of an instruction; and decoding, by the processing device, the instruction delta into a defined portion of the instruction to be used during execution of the instruction in place of the undefined portion.
Regarding the recited processing device in claim 19, Examiner notes that performing a mental process on a generic computer, performing a mental process in a computer environment, and using a computer as a tool to perform a mental process is still an abstract idea.
Regarding Eligibility Step 2A, Prong Two, the claim as a whole does not integrate the judicial exception into a practical application. In other words, the claim does not recite additional elements that integrate the judicial exception into a practical application. Regarding the recited “processing device” in claim 19, Examiner notes that merely reciting the words "apply it" (or an equivalent) with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using a computer as a tool to perform an abstract idea, or generally linking the use of a judicial exception to a particular technological environment or field of use, does not integrate a judicial exception into a practical application. Therefore, the claim is directed to the judicial exception.
Regarding Eligibility Step 2B, the claim does not recite additional elements that amount to an inventive concept. In other words, the claim does not recite additional elements that, individually or in combination, amount to significantly more than the judicial exception itself. Regarding the recited “processing device” in claim 19, Examiner notes that merely adding the words "apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception, e.g., a claim to an abstract idea requiring no more than a generic computer to perform generic computer functions that are well-understood, routine and conventional activities previously known to the industry, or generally linking the use of a judicial exception to a particular technological environment or field of use, are not enough to qualify as "significantly more" when recited in a claim with a judicial exception.
Claim 20 further recites executing the instruction based on the defined portion. However, this subject matter merely reflects a generic computer perform generic computer functions (e.g., executing an instruction based on the contents of the instruction), and further abstract ideas including mental processes (e.g., executing an instruction based on the contents of the instruction), and thus does not recite additional elements which could integrate the abstract idea into a practical application or provide significantly more than the abstract idea itself. Claim 20 also recites that the aforementioned processing device includes an in-memory processor. To any extent to which an “in-memory processor” is not encompassed by the previous mentions of, for example, a computer or computing environment, Examiner takes official notice of the well-understood, routine, conventional nature of an “in-memory processor”. Also note that CPC G06F15/7821 is directed to “computational memory, smart memory, processor in memory”, as are the previously cited pertinent prior art references Jayasena (US 20220413849 A1) (see [0001], “in-memory compute device”) and Alsop et al. (US 20210389907 A1) (see [0011], “processing-in-memory”). Therefore, this subject matter likewise does not integrate the abstract idea into a practical application or provide significantly more than the abstract idea itself.
Independent claim 1 is rejected for analogous reasons as claims 19 and 20 above. Claim 2 further limits the instruction of the abstract idea, which does not integrate the abstract idea into a practical application or provide significantly more than the abstract idea itself, and further recites registers; however, Examiner submits that registers are likewise components of a generic computer to perform generic computer functions. Claim 3 further limits the instruction of the abstract idea to a particular type of instruction, which does not integrate the abstract idea into a practical application or provide significantly more than the abstract idea itself, and further recites registers; however, Examiner submits that registers are likewise components of a generic computer to perform generic computer functions. Claim 4 merely limits the recited undefined portion of the abstract idea to particular types of fields, and therefore does not recite additional elements which could integrate the abstract idea into a practical application or provide significantly more than the abstract idea itself. Claim 5 merely limits the recited defined portion of the abstract idea to particular types of data, and therefore does not recite additional elements which could integrate the abstract idea into a practical application or provide significantly more than the abstract idea itself. Claim 6 further limits the instruction of the abstract idea to a particular type of instruction, which does not integrate the abstract idea into a practical application or provide significantly more than the abstract idea itself, and further recites registers; however, Examiner submits that registers are likewise components of a generic computer to perform generic computer functions. Claim 7 merely limits the recited undefined portion of the abstract idea to a particular type of field, and therefore does not recite additional elements which could integrate the abstract idea into a practical application or provide significantly more than the abstract idea itself. Claim 8 further limits the instruction of the abstract idea to a particular type of instruction and limits the recited undefined portion of the abstract idea to a particular type of field, which does not integrate the abstract idea into a practical application or provide significantly more than the abstract idea itself. Claim 8 also recites bank of memory; however, Examiner submits that memory banks are likewise components of a generic computer to perform generic computer functions. Claim 9 is rejected for analogous reasons a claim 20 above. Claim 10 further limits the recited undefined portion of the abstract idea to a particular type of field and the defined portion of the abstract idea to a particular values, which does not integrate the abstract idea into a practical application or provide significantly more than the abstract idea itself. Claim 10 also recites registers; however, Examiner submits that registers are likewise components of a generic computer to perform generic computer functions. Claim 10, in reciting coalescing the plurality of values during execution of the instruction, merely reflects further abstract ideas including mental processes in an analogous manner as claim 1 above.
Independent claim 11 is rejected for analogous reasons as claim 20 above. Claim 12 further recites a command buffer unit that maintains the PIM command including the instruction; however, Examiner notes that the courts have recognized storing and retrieving information in memory, as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. Claim 13 further recites receiving the PIM command including the instruction from a memory controller; however, Examiner notes that the courts have recognized receiving or transmitting data over a network, and storing and retrieving information in memory, as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. Examiner further submits that a memory controller is likewise a component of a generic computer to perform generic computer functions. Claim 17 recites further decoding, and therefore merely reflects further abstract ideas including mental processes in an analogous manner as claim 1 above. Examiner also notes that the courts have recognized receiving or transmitting data over a network and performing repetitive calculations as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity.
Response to Arguments
Applicant on page 11 argues: “The specification stands objected to by the Office for alleged informalities (Office Action, p. 2). Amendments to the specification are provided herein to address the informalities, and Applicant respectfully requests that the objection be withdrawn.”
In view of the aforementioned amendments, the previously presented objections to the specification are withdrawn.
Applicant on page 11 argues: ‘Claims 1-11, 13, and 17 are rejected under 35 U.S.C. 101 because the claimed invention is allegedly directed to non-statutory subject matter. The Office Action states that claim 1 "can be interpreted as software per se and thus can be made without an actual hardware apparatus" (Office Action, p. 14). Accordingly, claim 1 is amended to recite "a memory implemented in hardware of the system" and therefore cannot be interpreted as software per se. Accordingly, Applicant respectfully requests that the § 101 rejection be withdrawn.’
In view of the aforementioned amendments, the aforementioned software per se rejections are withdrawn.
Applicant on page 12 argues: “Claims 11, 13, and 17 are rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, because the claim purports to invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, but allegedly fails to recite a combination of elements as required by that statutory provision and thus cannot rely on the specification to provide the structure, material or acts to support the claimed function (Office Action, p. 6). Applicant amends the claims as indicated above to address these issues. Accordingly, Applicant respectfully requests that the §112(a) rejections are withdrawn.”
However, Examiner submits that the aforementioned rejections appear to remain applicable.
Applicant on page 12 argues: “Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement because the claim(s) are alleged to contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre- AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention (Office Action, p. 7). Applicant disagrees. Nevertheless, Applicant amends the claims as indicated above to address these issues. Accordingly, Applicant respectfully requests that the §112(a) rejections are withdrawn.”
In view of the aforementioned amendments, the previously presented rejections under 35 U.S.C. 112(a) are withdrawn.
Applicant across pages 12-13 argues: “Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as allegedly being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention (Office Action, p. 9). Applicant amends the claims as indicated above to address these issues. Accordingly, Applicant respectfully requests that the §112(b) rejections are withdrawn.”
In view of the aforementioned amendments, the previously presented rejections under 35 U.S.C. 112(b) are withdrawn.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. (Examiner also notes that the prior art set forth across pages 21-24 of the office action dated June 12, 2025, remains pertinent for the reasons conveyed.)
Toll et al. (US 20150186140 A1) discloses “Mask register 240 may be a programmable register available for software to use according to an embodiment of the present invention to hold a mask with which to determine which portion of instruction register 230 is to be used for trapping. … For example, the current opcode (or a portion thereof) may be selected by programming mask register 240 with all ones in opcode mask 242 (or a portion thereof) and all zeroes in operand mask 244. Similarly, one or more current operands (or portions thereof) may be selected by programming mask register 240 with all ones in that portion of operand mask 244 to be selected and all zeroes in the remainder of mask register 240” (see paragraph [0025]), discloses “Handling of opcode traps by opcode trap handler 330 may include implementing updates, workarounds or bug fixes, adding new capabilities or functionality, implementing security, virtualization, system management, or other features, emulating or otherwise performing the function of a microcode patch, and/or any other desired actions” (see paragraph [0027]), and discloses “opcode trap handler 330 handles the opcode trap, for example, by invoking one or more instructions to replace the trapped instruction” (see paragraph [0036]), which is relevant to the claimed us[ing] in place, opcode, and operands.
Richter et al. (US 5481684) discloses “Undefined opcodes force the CPU into emulation mode, where the emulation driver executes the appropriate error routine” in col. 12, lines 53-55, which is relevant to the claimed undefined portion of the instruction, us[ing] in place of the undefined portion, and opcode.
Shiell et al. (US 6049672) discloses ‘once a microprocessor is manufactured and distributed, a discovery of one more erroneous values for either or both of the micro-operation codes and the microinstructions must be addressed. In this regard, some prior art systems include architectures which permit correction by replacement, or so-called "patching", of the micro-operation codes and microinstruction codes. Patching operates so that the system, in whatever manner, substitutes a new bit pattern (i.e., either a new micro-operation code or a new microinstruction code) in place of the erroneous one, thereby correcting system operation’ (see col. 1, line 58, to col. 2, line 1), which is relevant to the claimed us[ing] in place.
Dong (US 20080282241 A1) discloses “a pseudo instruction is an instruction that is undefined or that includes an invalid argument or value. Consequently, when a pseudo instruction from an emulation patch (i.e., a patched pseudo instruction) is executed, it will trigger a fault (e.g., an illegal operation fault)” (see paragraph [0012] and “determine which guest instruction corresponds to the pseudo instruction that caused the fault, and to then emulate that guest instruction” (see paragraph [0014]), which is relevant to the claimed undefined portion of the instruction, and us[ing] in place of the undefined portion.
Yeh et al. (US 6282636 B1) discloses “an architectural exception is raised when an instruction tries to access an address that is not present in memory or the processor attempts to execute an undefined opcode. For these architectural exceptions, the processor intervenes and transfers control to a handler that addresses the triggering event” (see col. 1, lines 37-43), which is relevant to the claimed undefined portion of the instruction, and us[ing] in place of the undefined portion and opcode.
Johnson et al. (US 7831807 B1) discloses “In most instruction processors, an interrupt is generated to the operating system when an undefined (invalid) instruction opcode is encountered. The operating system will generally recognize this as an error condition. If desired, one of these previously undefined opcodes may be selected to designate a newly defined or modified instruction. When an interrupt is generated to the operating system upon encountering this opcode, the operating system can be used to identify this opcode as a valid instruction. The operating system then emulates the newly defined instruction in software. That is, multiple software instructions are executed to emulate the functions that would otherwise be performed in hardware and/or microcode if the instruction opcode were part of the IP's instruction set” (see col. 1, lines 52-65), which is relevant to the claimed undefined portion of the instruction, us[ing] in place of the undefined portion, and opcode.
Mahalingaiah et al. (US 5983337) discloses “Instructions detected by prefetch/predecode unit 12 as instructions to be patched will match an opcode stored in the patch opcode register of MROM unit 34. If the instruction opcode matches one of the opcodes in the patch opcode register, MROM unit 34 invokes a patch microcode routine. The patch microcode routine dispatches a plurality of microcode instructions that cause a substitute instruction to be read (see col. 5, lines 58-65), which is relevant to the claimed us[ing] in place and opcode.
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/KEITH E VICARY/ Primary Examiner, Art Unit 2183