DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending and examined.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-13, 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by PGPub. 2015/0287458 to Pellizzer et al. (hereafter Pellizzer).
Regarding independent claim 1, Pellizzer teaches an apparatus comprising:
a memory array comprising a first memory cell comprising a first two terminal element having a first threshold voltage and a second threshold voltage (FIG. 6: reference cell 2a comprising ovonic switch 4a and memory element 3a, which has first and second threshold voltages corresponding to set and reset states), and a second memory cell comprising a second two-terminal element having a third threshold voltage and a fourth threshold voltage (FIG. 6: memory cell 2 comprising ovonic switch 4 and memory element 3, which has third and fourth threshold voltages corresponding to set and reset states); and
an inherent control circuit coupled to the memory array (for controlling operation of memory array of FIG. 6), the control circuit configured to:
apply a first voltage signal to the first memory cell to cause the first two-terminal element to have the first threshold voltage (during programming, the reference cell 2a is programmed to set state, see paragraph [0053]);
apply a second voltage signal to the second memory cell to cause the second two-terminal element to have either the third threshold voltage or the fourth threshold voltage (during programming, the memory cell 2 is programmed to set or reset state, see paragraph [0053]);
apply a third voltage signal to the first memory cell and the second memory cell, the third voltage signal increasing at a first ramp rate (during reading, word line coupled to reference cell 2a receives a ramp voltage, see paragraph [0051]);
determine that the first memory cell switches from a non-conducting state to a conducting state (FIG. 6: when the switching detector 66 detects a current through reference bitline 5a exceed a preset reference value, see paragraph [0057]); and
read the second memory cell using the third voltage signal a first predetermined delay time after the first memory cell switches from the nonconducting state to the conducting state (when the switching of reference cell 2a is detected, after a small and pre-defined delay, stop voltage ramp on the word line 6 and read memory cells 2, see paragraph [0051], and use the voltage ramp to read memory cell 2).
Regarding dependent claim 3, Pellizzer teaches wherein the control circuit is further configured to cause the third voltage signal to stop increasing at the first predetermined delay time after the first memory cell switches from the non-conducting state to the conducting state (see paragraph [0051]).
Regarding dependent claim 4, Pellizzer teaches wherein: the first memory cell is configured to be read using a read voltage comprising a first polarity; and the first two-terminal element has the first threshold voltage when the first memory cell was previously written using a write signal comprising the first polarity, and has the second threshold voltage when the first memory cell was previously written using a write signal comprising a second polarity opposite the first polarity (see entire disclosure of US 3,271,591, which is incorporated by reference, see paragraphs [0015], [0017]).
Regarding dependent claim 5, Pellizzer teaches wherein: the second memory cell is configured to be read using a read voltage comprising the first polarity; and the second two-terminal element has the third threshold voltage when the second memory cell was previously written using a write signal comprising the first polarity, and has the fourth threshold voltage when the second memory cell was previously written using a write signal comprising the second polarity (see entire disclosure of US 3,271,591, which is incorporated by reference, see paragraphs [0015], [0017]).
Regarding dependent claim 6, Pellizzer teaches wherein: the first threshold voltage and the third threshold voltage comprise a first threshold voltage distribution (); and the second threshold voltage and the fourth threshold voltage comprises a second threshold voltage distribution (FIG. 6: memory elements 3a and 3 have first/third and second/fourth threshold voltages corresponding to set and reset states).
Regarding dependent claim 7, Pellizzer teaches wherein: the first threshold voltage is lower than the second threshold voltage; and the third threshold voltage is lower than the fourth threshold voltage (because set state has threshold voltage lower than that of reset states).
Regarding dependent claim 8, Pellizzer teaches wherein: the first threshold voltage and the second threshold voltage drift after the first memory cell is written; and the third threshold voltage and the fourth threshold voltage drift after the second memory cell is written (see paragraph [0026]-[0034]).
Regarding dependent claim 9, Pellizzer teaches wherein the first threshold voltage, the second threshold, the third threshold voltage and the fourth threshold voltage drift at substantially a same rate (see paragraphs [0052]-[0053]).
Regarding dependent claim 10, Pellizzer teaches wherein the first two-terminal element and the second two-terminal element each comprise a selector material that provides a bidirectional current flow when the current or voltage exceeds a threshold value (see entire disclosure of US 3,271,591, which is incorporated by reference, see paragraphs [0015], [0017]).
Regarding dependent claim 11, Pellizzer teaches wherein the first two-terminal element and the second two-terminal element each comprise a chalcogenide material (see paragraph [0026]).
Regarding dependent claim 12, Pellizzer teaches wherein the first two-terminal element and the second two-terminal element each comprise one or more of a GeSeAs alloy, a GeSeAsTe alloy, a GeTeAs alloy, a GeSeTe alloy, a GeSe alloy, a SeAs alloy, a AsTe alloy, a GeTe alloy, a SiTe alloy, a SiAsTe alloy, and a SiAsSe alloy (see paragraph [0002]).
Regarding dependent claim 13, Pellizzer teaches wherein the first two-terminal element and the second two-terminal element each comprise an ovonic threshold switch (see paragraph [0045]).
Regarding independent claim 20, Pellizzer teaches a method comprising:
writing a reference memory cell to a first memory state (during programming, the reference cell 2a is programmed to set state, see paragraph [0053]) and writing data to a plurality of data memory cells (during programming, the memory cell 2 is programmed to set or reset state, see paragraph [0053]), the reference memory cell and the data memory cells each comprising an ovonic threshold switch, the ovonic threshold switches comprising a first threshold voltage distribution and a second threshold voltage distribution (FIG. 6: ovonic switches 4a and 4, each has first and second threshold voltages corresponding to set and reset states);
applying a ramping voltage to word lines coupled to the reference memory cell and the data memory cells (during reading, word line coupled to reference cell 2a receives a ramp voltage, see paragraph [0051]);
determining that the reference memory cell has switched from a nonconducting state to a conducting state (FIG. 6: when the switching detector 66 detects a current through reference bitline 5a exceed a preset reference value, see paragraph [0057]);
stopping the ramping voltage a first predetermined delay time after the reference memory cell switched from the non-conducting state to the conducting state (when the switching of reference cell 2a is detected, after a small and pre-defined delay, stop voltage ramp on the word line 6 and read memory cells 2, see paragraph [0051]); and
reading the plurality of data memory cells at the stopped ramp voltage (see paragraph [0051]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Pellizzer in view of US 11,282,571 to Mirichigni et al. (hereafter Mirichigni).
Pellizzer teaches, as applied in prior rejection of claim 1, all claimed subject matter except further limitations set forth in the following claim(s).
Regarding dependent claim 2, Mirichigni teaches a memory device comprising a plurality of memory cells (see FIG. 1). Each memory cell comprise a non-Ohmic element as selector device (FIG. 2: element 220, see 9:23-43) and a variable element as storage device (FIG. 2: element 210). Mirichigni further teaches a control circuit (FIG. 1: memory controller 140) configured to apply a [third] voltage to the word line of the memory cell during an auto-reference read, wherein the control circuit is further configured to cause the third voltage signal to change to a second ramp rate inherently lower than the first ramp rate when the first memory cell switches from the non-conducting state to the conducting state (i.e. read voltage has a monotonically increasing stair case shape, see 3:23-43. The second ramp rate is seen lower than the first ramp rate because after the resistance memory cell(s) is snapped, i.e. turned on, it conducts a larger current, the voltage applied should be kept at lower ramping rate to avoid steep increasing in current).
Since Pellizzer and Mirichigni are both from the same field of endeavor, the purpose disclosed by Mirichigni would have been recognized in the pertinent art of Pellizzer.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to apply the third voltage with different rates at different timing as suggested in Mirichigni to the memory device of Pellizzer because it is matter of design choice (see 3:23-43).
Claims 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over US 11,004,508 to Grobis et al. (hereafter Grobis) in view of Pellizzer.
Regarding dependent claim 14, Grobis teaches a system comprising:
a plurality of data modules (FIG. 5A: plurality data arrays 5011-502N), each data module comprising a plurality of data memory cells, each data memory cell comprising an ovonic threshold switch (FIG. 2B: selector Sx), the ovonic threshold switches comprising a first threshold voltage distribution and a second threshold voltage distribution (i.e. binary, see 7:42-51);
a first reference module that includes a first plurality of first reference memory cells (FIG. 5A: read ref array 5061), each first reference memory cell comprising an ovonic threshold switch (FIG. 2B: selector Sx) comprising a first reference threshold voltage distribution (corresponding to selector Sx of ref array 5061);
a plurality of word lines coupled to the plurality of data memory cells and the first plurality of first reference memory cells (FIG. 5A: word lines of access block 510);
an inherent voltage ramp control circuit coupled to the plurality of data modules and the first reference module, the voltage ramp control circuit configured to generate a ramping output voltage (for generating voltage ramp applied to selected memory cells of the access block, see 15:37-47); and
a control circuit (FIG. 1B: memory core controller circuits 108) coupled to the plurality of data modules, the first reference module and the voltage ramp control circuit, the control circuit configured to:
couple the ramping output voltage to a selected data memory cell from each of the plurality of data modules and a selected first reference memory cell from the first reference module (see FIG. 6A and 15:37-16:22);
determine that the selected first reference memory cell switches from a non-conducting state to a conducting state (see FIG. 6A and 15:37-16:22); and
first read each of the selected data memory cells using a voltage, wherein the voltage is calculated based the ramping output voltage after the selected first reference memory cell switches from the non-conducting state to the conducting state (i.e. when Sx of ref array 5061 turns on, see 16:1-12).
Grobis teaches the voltage is calculated based on the ramping output voltage instead of the ramping output voltage itself with a first predetermined delay time after the select reference memory cell switches from non-conducting state to conducting state.
Pellizzer teaches a read voltage is determined with a first predetermined delay time after the first memory cell switches from the nonconducting state to the conducting state (when the switching of reference cell 2a is detected, after a small and pre-defined delay, stop voltage ramp on the word line 6 and read memory cells 2, see paragraph [0051]).
Since Grobis and Pellizzer are both from the same field of endeavor, the purpose disclosed by Pellizzer would have been recognized in the pertinent art of Grobis.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to realize that the method of determining the read voltage in Grobis is functional equivalent to that of Pellizzer, because both approaches intend to find the mid-point value of read window between two threshold distribution for optimal reading.
Regarding dependent claim 15, Grobis teaches a second reference module that includes a second plurality of second reference memory cells (FIG. 5A: ref array 5062), each second reference memory cell comprising an ovonic threshold switch (FIG. 2B: selector Sx of ref array 5062) comprising a second reference threshold voltage distribution (corresponding to selector Sx of ref array 5061), wherein the control circuit is further configured to: couple the ramping output voltage to a selected second reference memory cell from the second reference module (see FIG. 6A and 15:37-16:22); determine that the selected first reference memory cell switches from a non-conducting state to a conducting state; and second read each of the selected data memory cells using the ramping output voltage a first predetermined delay time after the selected second reference memory cell switches from the non-conducting state to the conducting state (because read reference memory cells 510c1, and 510c2 have distinct voltage values V1 and V2 in response to the same ramp voltage, see 15:57-67).
Regarding dependent claim 16, Grobis teaches wherein the second read occurs before the first read (e.g. when V2<V2).
Regarding dependent claim 17, Grobis implicitly teaches wherein the first read comprises a first error rate and the second read comprises a second error rate higher than the first error rate (because when V2<V1, V2 is farther from mid-point value compare to V1, and therefore higher error rate).
Regarding dependent claim 18, Pellizzer teaches wherein each ovonic threshold switch comprises a chalcogenide material (see paragraph [0026]).
Regarding dependent claim 19, Pellizzer teaches wherein each ovonic threshold switch comprises one or more of a GeSeAs alloy, a GeSeAsTe alloy, a GeTeAs alloy, a GeSeTe alloy, a GeSe alloy, a SeAs alloy, a AsTe alloy, a GeTe alloy, a SiTe alloy, a SiAsTe alloy, and a SiAsSe alloy (see paragraph [0002]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
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May 16, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
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