DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This Office Action is sent in response to Applicant’s Communication received 6/28/2024 for application number 18/758,300. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, claims.
3. Claims 1 – 20 are presented for examination.
Claim Rejections - 35 USC § 112
4. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
5. Claim 11 recites the limitation "the integrated circuit” at line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
8. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
9. Claims 1, 10 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Champigny (U.S. Publication 2020/0183738) (Champigny hereinafter) in view of Nemlekar et al. (U.S. Publication 2022/0319089) (Nemlekar hereinafter).
10. As per claim 1, Champigny teaches an integrated circuit, comprising:
multiple compute tiles that comprise respective compute cores, program
memory, and local data memory [“A method includes: forming a virtual tile cluster having tiles, wherein a tile comprises a processor and memory from a CPU device and a GPU device, and a tile in the GPU device further comprises subprocessors; forming a virtual unified memory that is accessible by the CPU and GPU devices,” Abstract; subprocessors mapped to compute cores; “FIGS. 5 and 6 are flow diagrams illustrating the processing performed by the CPU runtime and GPU runtime (e.g., 210 and 230 in FIG. 2). Rectangular elements (typified by element 510 in FIG. 3), herein denoted “processing blocks,” represent computer software instructions or groups of instructions and diamond shaped elements (not shown), herein denoted decision blocks represent computer software instructions or groups of instructions which affect the flow of the processing blocks. The processing blocks may represent steps performed by functionally equivalent circuits such as a digital signal processor (DSP) circuit or an application specific integrated circuit (ASIC),” ¶ 0063]; and
a first lead dispatch node comprising one or more of dedicated hardware
and one of the compute tiles [“The GPU scheduler 232 may bypass the hardware scheduler provided by the manufacturer of the GPU (e.g., NVIDIA GPU scheduler). In embodiments, the GPU scheduler 232 may launch as many threads as necessary to implement the number of tiles in a chosen tile configuration. Those threads may be further partitioned into warp-sized tiles. In some embodiments, the GPU scheduler 232 may place the first thread of each tile, called the leader, in charge of interacting with an ingress ring 252. The leader may consume tasks from the ingress ring 252 and then dispatch on the task opcode to the appropriate task codelet,” ¶ 0054];
wherein, the compute cores are configured to access the program memories,
the local data memories, and local data memory pools of the respective
compute tiles [“each of the warp-sized tiles may form a tile engine 162 in the virtual tile cluster 160. Each tile engine 162 may be viewed as a vector processor with 32-lanes of scalar processing elements, where the scalar processing elements 166 are considered as subprocessors. In some embodiments, a tile may have more or less than 32-lanes of scalar processing elements. These lanes have more autonomy than traditional vector lanes on a CPU since their control flow can diverge and the tile engines can access disjoint memory (i.e., distributed scratchpad memory 164 or the GPU global memory) on the GPU,” ¶ 0039; scratchpad memory mapped to local memory pools];
the local data memory pools each comprise the local data memory
of the respective compute tile and the local data memory of one or more
other ones of the compute tiles [“developers may be required to choose which offload engine they will use. In some embodiments, the two mechanisms may be merged to offer the same tile and local memory abstraction. Herein, the CPU runtime 310 may present CPU cores as tiles with 1-lane vector processors (effectively scalar processors). Additionally, a shared memory in the CPU runtime 210 may emulate the concept of a scratchpad memory in the GPU runtime 230,” ¶ 0057], and
the first lead dispatch node is configured to dynamically assign a
first task of an application to a selected one of the compute tiles [“When a task arrives at an input channel (processing step 540), the CPU runtime may assign the task to at least one tile in the virtual tile cluster,” ¶ 0064].
Nemlekar discloses route a corresponding first active message to the local data memory pool of the selected compute tile, wherein the first active message comprises
instructions and data to enable the selected compute tile to execute the
first task [“A command processor 136 performs operations related to scheduling various workgroups on different compute units 132 and SIMD units 138. In general, the command processors 136 receive commands from an entity such as the processor 102, where the commands instruct the chiplets 201 to perform tasks such as graphics rendering, executing general purpose shaders, or the like,” ¶ 0017; chiplet mapped to tile].
It would have been obvious to one of ordinary skill in the art, having the teachings of Champigny and Nemlekar available before the effective filing date of the claimed invention, to modify the capability of managing a virtual tile cluster as disclosed by Champigny to include the capability of controlling execution of tasks on tiles/chiplets as taught by Nemlekar, thereby providing a mechanism to enhance system efficiency by managing task execution in a multi-resource environment.
11. As per claim 10, Champigny teaches a non-transitory computer readable medium encoded with a computer program that comprises instructions to cause a processor to: compile an application to execute on a spatial compute architecture that comprises multiple compute tiles that comprise respective compute cores, program memory, and local data memory [“A method includes: forming a virtual tile cluster having tiles, wherein a tile comprises a processor and memory from a CPU device and a GPU device, and a tile in the GPU device further comprises subprocessors; forming a virtual unified memory that is accessible by the CPU and GPU devices,” Abstract; subprocessors mapped to compute cores; “FIGS. 5 and 6 are flow diagrams illustrating the processing performed by the CPU runtime and GPU runtime (e.g., 210 and 230 in FIG. 2). Rectangular elements (typified by element 510 in FIG. 3), herein denoted “processing blocks,” represent computer software instructions or groups of instructions and diamond shaped elements (not shown), herein denoted decision blocks represent computer software instructions or groups of instructions which affect the flow of the processing blocks. The processing blocks may represent steps performed by functionally equivalent circuits such as a digital signal processor (DSP) circuit or an application specific integrated circuit (ASIC),” ¶ 0063; “with requesting execution of the kernels . In embodiments , a kernel is implemented as a “ codelet which refers a small and simple procedure , program or application compiled and executed on the GPU,” ¶ 0042], and that further comprises a first lead dispatch node that comprises one or more of dedicated hardware and one of the compute tiles [“The GPU scheduler 232 may bypass the hardware scheduler provided by the manufacturer of the GPU (e.g., NVIDIA GPU scheduler). In embodiments, the GPU scheduler 232 may launch as many threads as necessary to implement the number of tiles in a chosen tile configuration. Those threads may be further partitioned into warp-sized tiles. In some embodiments, the GPU scheduler 232 may place the first thread of each tile, called the leader, in charge of interacting with an ingress ring 252. The leader may consume tasks from the ingress ring 252 and then dispatch on the task opcode to the appropriate task codelet,” ¶ 0054], wherein the compute cores are configured to access the program
memories, the local data memories, and local data memory pools of the
respective compute tiles [“each of the warp-sized tiles may form a tile engine 162 in the virtual tile cluster 160. Each tile engine 162 may be viewed as a vector processor with 32-lanes of scalar processing elements, where the scalar processing elements 166 are considered as subprocessors. In some embodiments, a tile may have more or less than 32-lanes of scalar processing elements. These lanes have more autonomy than traditional vector lanes on a CPU since their control flow can diverge and the tile engines can access disjoint memory (i.e., distributed scratchpad memory 164 or the GPU global memory) on the GPU,” ¶ 0039; scratchpad memory mapped to local memory pools], and wherein the local data memory pools each comprise the local data memory of the respective compute tile and the local data memory of one or more other ones of the compute tiles [“developers may be required to choose which offload engine they will use. In some embodiments, the two mechanisms may be merged to offer the same tile and local memory abstraction. Herein, the CPU runtime 310 may present CPU cores as tiles with 1-lane vector processors (effectively scalar processors). Additionally, a shared memory in the CPU runtime 210 may emulate the concept of a scratchpad memory in the GPU runtime 230,” ¶ 0057], including to compile the application such that, the first lead dispatch node dynamically assigns a first task of the
application to a selected one of the compute tiles [“When a task arrives at an input channel (processing step 540), the CPU runtime may assign the task to at least one tile in the virtual tile cluster,” ¶ 0064].
Champigny does not explicitly disclose but Nemlekar discloses routes a corresponding first active message to the local data memory pool of the selected compute tile, wherein the first active message comprises instructions and data to enable the selected compute tile to execute the first task [“A command processor 136 performs operations related to scheduling various workgroups on different compute units 132 and SIMD units 138. In general, the command processors 136 receive commands from an entity such as the processor 102, where the commands instruct the chiplets 201 to perform tasks such as graphics rendering, executing general purpose shaders, or the like,” ¶ 0017; chiplet mapped to tile].
It would have been obvious to one of ordinary skill in the art, having the teachings of Champigny and Nemlekar available before the effective filing date of the claimed invention, to modify the capability of managing a virtual tile cluster as disclosed by Champigny to include the capability of controlling execution of tasks on tiles/chiplets as taught by Nemlekar, thereby providing a mechanism to enhance system efficiency by managing task execution in a multi-resource environment.
12. As per claim 16, it is a method claim having similar limitations as cited in claim 10. Thus, claim 16 is also rejected under the same rationale as cited in the rejection of claim 10 above.
13. Claims 2, 3, 7, 8, 11, 14, 15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Champigny and Nemlekar in further view of Wu et al. (U.S. Patent 11,068,641) (Wu hereinafter).
14. As per claim 2, Champigny and Nemlekar teach the integrated circuit of claim 1. Champigny further teaches wherein: the integrated circuit further comprises a shared memory tile that is accessible to the compute tiles, and configurable interconnect structures [“A GPU may have any number of multi-processors and each of the multi-processors has a dedicated scratchpad memory to be shared by the subprocessors (i.e., lanes). This type of scratchpad memory is sometimes called a shared memory, which has a different meaning from when the term “shared memory” is used for a CPU device,” ¶ 0036].
Champigny and Nemlekar do not explicitly disclose but Wu discloses the first lead dispatch node is further configured to route the first active message to the local data memory pool of the selected compute tile from one of the shared memory tile and an external memory [“tasks may execute on tiled compute units, and tasks may communicate with each other by reading and writing data to a shared buffer or to a memory having a communal data buffer accessible by a plurality of distinct computing tiles on the integrated circuit. In such embodiments, tasks may have data dependencies that may need to be met before the task can execute and tasks may need to schedule access to the shared buffers in order to satisfy data dependencies,” col. 16, lines 17 – 25].
It would have been obvious to one of ordinary skill in the art, having the teachings of Champigny, Nemlekar and Wu available before the effective filing date of the claimed invention, to modify the capability of managing a virtual tile cluster as disclosed by Champigny and Nemlekar to include the capability of optimizing data flow within an integrated circuit architecture as taught by Wu, thereby providing a mechanism to enhance system efficiency by managing data exchanges in a multi-resource environment.
15. As per claim 3, Champigny, Nemlekar and Wu teach the integrated circuit of claim 2. Champigny further teaches wherein: the first active message further comprises configuration data to enable the selected compute tile to execute the first task [“The GPU runtime 330 may provide abstract concepts such as tiles 352, 354 with local memories instead of physical GPU device features such as warps, SMs, scratch pad memories, or scalar cores. In some embodiments, a subset of the total number of tiles available called a "slice' may be used. The slice may be composed of from one to the maximum number of tiles available on the GPU runtime 330 according to a configuration. Herein, the GPU runtime 330 executes codelets on the slice, not on a tile beyond the slice,” ¶ 0061].
16. As per claim 7, Champigny and Nemlekar teach the integrated circuit of claim 1. Champigny further teaches a second lead dispatch node, wherein: the first lead dispatch node is configured to dynamically assign the first task to a selected compute tile of a first set of the compute tiles; the second lead dispatch node is configured to dynamically assign a second task of the application to a selected compute tile of a second set of the compute tiles, and to route a corresponding second active message to the local data memory pool of the selected compute tile of the second set of compute tiles [“When a task arrives at an input channel (processing step 540), the CPU runtime may assign the task to at least one tile in the virtual tile cluster,” ¶ 0064; “FIG. 4 presents exemplary tile con figurations assuming a hypothetical GPU with 3 SMs. The first configuration 410 may maximize the scratch - pad memory per tile at the cost of reduced throughput capacity. Herein, one tile is enabled per SM while this configuration could leave several warps worth of scalar cores unused in the SM. The second configuration 420 may create as many tiles as possible to exactly cover the number of scalar cores on each SM,” ¶ 0062].
Wu further teaches the first lead dispatch node is further configured to dynamically assign the first task to the second lead dispatch node if the first task is declined by one or more of the compute tiles of the first set of compute tiles [“tasks may execute on tiled compute units, and tasks may communicate with each other by reading and writing data to a shared buffer or to a memory having a communal data buffer accessible by a plurality of distinct computing tiles on the integrated circuit. In such embodiments, tasks may have data dependencies that may need to be met before the task can execute and tasks may need to schedule access to the shared buffers in order to satisfy data dependencies,” col. 16, lines 17 – 25].
It would have been obvious to one of ordinary skill in the art, having the teachings of Champigny, Nemlekar and Wu available before the effective filing date of the claimed invention, to modify the capability of managing a virtual tile cluster as disclosed by Champigny and Nemlekar to include the capability of optimizing data flow within an integrated circuit architecture as taught by Wu, thereby providing a mechanism to enhance system efficiency by managing data exchanges in a multi-resource environment.
17. As per claim 8, Champigny, Nemlekar and Wu teach the integrated circuit of claim 7. Wu further teaches wherein: the first lead dispatch node is further configured to route the first active message to the second lead dispatch node via a pooled synchronized circular buffer that is accessible to the first and second lead dispatch nodes [“each of a first dependent task and a second dependent task of a distinct pair dependent tasks of the plurality of distinct pairs of dependent tasks interface through the respective data buffer allocated between the distinct pair of dependent tasks,” col. 4, lines 2 – 6; “variations of a physical buffer may be implemented for communication between tasks, including but not limited to a circular buffer and a line buffer. A circular buffer preferably relates to a physical buffer with head and tail indices where elements are added to the head of the physical buffer and removed from the tail of the physical buffer,” col. 15, lines 5 – 11].
It would have been obvious to one of ordinary skill in the art, having the teachings of Champigny, Nemlekar and Wu available before the effective filing date of the claimed invention, to modify the capability of managing a virtual tile cluster as disclosed by Champigny and Nemlekar to include the capability of optimizing data flow within an integrated circuit architecture as taught by Wu, thereby providing a mechanism to enhance system efficiency by managing data exchanges in a multi-resource environment.
18. As per claim 11, it is a media claim having similar limitations as cited in claim 2. Thus, claim 11 is also rejected under the same rationale as cited in the rejection of claim 2 above.
19. As per claim 14, it is a media claim having similar limitations as cited in claim 7. Thus, claim 14 is also rejected under the same rationale as cited in the rejection of claim 7 above.
20. As per claim 15, it is a media claim having similar limitations as cited in claim 8. Thus, claim 15 is also rejected under the same rationale as cited in the rejection of claim 8 above.
21. As per claim 17, it is a method claim having similar limitations as cited in claim 2. Thus, claim 17 is also rejected under the same rationale as cited in the rejection of claim 2 above.
22. Claims 4, 12 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Champigny and Nemlekar in further view of Wu, Parikh et al. (U.S. Patent 11,016,810) (Parikh hereinafter) and Ramesh et al. (U.S. Publication 2020/0387444) (Ramesh hereinafter).
23. As per claim 4, Champigny and Nemlekar teach the integrated circuit of claim 1. Wu further teaches the first lead dispatch node is further configured to route the first active message to the available space of the local data memory pool of the selected
compute tile based on the identifier [“tasks may execute on tiled compute units, and tasks may communicate with each other by reading and writing data to a shared buffer or to a memory having a communal data buffer accessible by a plurality of distinct computing tiles on the integrated circuit. In such embodiments, tasks may have data dependencies that may need to be met before the task can execute and tasks may need to schedule access to the shared buffers in order to satisfy data dependencies,” col. 16, lines 17 – 25].
It would have been obvious to one of ordinary skill in the art, having the teachings of Champigny, Nemlekar and Wu available before the effective filing date of the claimed invention, to modify the capability of managing a virtual tile cluster as disclosed by Champigny and Nemlekar to include the capability of optimizing data flow within an integrated circuit architecture as taught by Wu, thereby providing a mechanism to enhance system efficiency by managing data exchanges in a multi-resource environment.
Champigny, Nemlekar and Wu do not explicitly disclose but Parikh discloses wherein: the first lead dispatch node is further configured to query the compute core of the selected compute tile to determine if the local data memory pool of the selected compute tile has available space for the first active message [“a mixed-signal computing tile array may have a number of challenges which may include how to assign a given task to the limited computing resources (e.g., available processing, memory, etc.), limited communication bandwidth between tiles, managing data flow of concurrent running tasks, determining when the dependencies for a task may have been met which may be a prerequisite of the task being able to execute, and decomposing tasks too large to fit into a single tile such that the task may be divided among multiple tiles and the resultant outputs combined,” col. 7, lines 1 – 11].
It would have been obvious to one of ordinary skill in the art, having the teachings of Champigny, Nemlekar, Wu and Parikh available before the effective filing date of the claimed invention, to modify the capability of managing a virtual tile cluster as disclosed by Champigny, Nemlekar and Wu to include the capability of managing automated data flow within an integrated circuit architecture as taught by Parikh, thereby providing a mechanism to enhance system efficiency by managing data exchanges in a multi-resource environment.
Champigny, Nemlekar, Wu and Parikh do not explicitly disclose but Ramesh discloses the compute core of the selected compute tile is further configured to accept the first task and provide an identifier of the available space to the first lead dispatch node if the local data memory pool of the selected compute tile has
the available space for the first active message [“the computing tile 110 that contains the data that is requested for performance of an extended memory operation can be determined by the host controller 101, the orchestration controller 106, and/or the control NoC 108-1 and data NoC 108-2. For example, a portion of a total address space available to all the computing tiles 110 can be allocated to each respective computing tile. Accordingly, the host controller 101, the orchestration controller 106, and/or the control NoC 108-1 and data NoC 108-2 can be provided with information corresponding to which portions of the total address space correspond to which computing tiles 110 and can therefore direct the relevant computing tiles 110 to perform extended memory operations. In some embodiments, the host controller 101, the orchestration controller 106, and/or the control NoC 108-1 and data NoC 108-2 can store addresses (or address ranges) that correspond to the respective computing tiles 110 in a data structure, such as a table, and direct performance of the extended memory operations to the computing tiles 110 based on the addresses stored in the data structure,” ¶ 0051].
It would have been obvious to one of ordinary skill in the art, having the teachings of Champigny, Nemlekar, Wu, Parikh and Ramesh available before the effective filing date of the claimed invention, to modify the capability of managing a virtual tile cluster as disclosed by Champigny, Nemlekar, Wu and Parikh to include the capability of managing an extended memory interface as taught by Ramesh, thereby providing a mechanism to enhance system efficiency by managing data access to available memory resources.
24. As per claim 12, it is a media claim having similar limitations as cited in claim 4. Thus, claim 12 is also rejected under the same rationale as cited in the rejection of claim 4 above.
25. As per claim 18, it is a method claim having similar limitations as cited in claim 4. Thus, claim 18 is also rejected under the same rationale as cited in the rejection of claim 4 above.
26. As per claim 5, Champigny, Nemlekar, Wu, Ramesh and Parikh teach the integrated circuit of claim 4. Wu discloses the first lead dispatch node is further configured to route the first active message to one of a shared memory tile and the local data memory pool of another one of the compute tiles if the compute core of the selected compute tile declines the first task; and the first lead dispatch node is further configured to route the first active message to the local data memory pool of the selected compute tile when the local data memory pool of the selected compute tile has the available space for the first active message [“tasks may execute on tiled compute units, and tasks may communicate with each other by reading and writing data to a shared buffer or to a memory having a communal data buffer accessible by a plurality of distinct computing tiles on the integrated circuit. In such embodiments, tasks may have data dependencies that may need to be met before the task can execute and tasks may need to schedule access to the shared buffers in order to satisfy data dependencies,” col. 16, lines 17 – 25].
It would have been obvious to one of ordinary skill in the art, having the teachings of Champigny, Nemlekar and Wu available before the effective filing date of the claimed invention, to modify the capability of managing a virtual tile cluster as disclosed by Champigny and Nemlekar to include the capability of optimizing data flow within an integrated circuit architecture as taught by Wu, thereby providing a mechanism to enhance system efficiency by managing data exchanges in a multi-resource environment.
Rao discloses the compute core of the selected compute tile is further configured to decline the first task if the local data memory pool of the selected compute tile
lacks the available space for the first active message [“denying the kernel client's request if there is insufficient free memory in the first kernel memory resource group to accommodate the kernel client's request,” ¶ 0020].
27. Claims 6 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Champigny and Nemlekar in further view of Livesley et al. (U.S. Publication 2023/0410243) (Livesley hereinafter).
28. As per claim 6, Champigny and Nemlekar teach the integrated circuit of claim 1. Livesley discloses wherein the first lead dispatch node is further configured to: dynamically select one of the compute tiles as the selected compute tile based on pending tasks of the compute tiles [“By assigning a new task to the core with the fewest pending tasks, as indicated by the credit numbers of the cores, the master unit can avoid loading one core with work while another core runs out of work and possibly becomes idle,” ¶ 0030].
It would have been obvious to one of ordinary skill in the art, having the teachings of Champigny, Nemlekar and Livesley available before the effective filing date of the claimed invention, to modify the capability of managing a virtual tile cluster as disclosed by Champigny and Nemlekar to include the capability of task to core assignment as taught by Livesley, thereby providing a mechanism to enhance system efficiency by managing available core resources.
29. As per claim 20, it is a method claim having similar limitations as cited in claim 6. Thus, claim 20 is also rejected under the same rationale as cited in the rejection of claim 6 above.
Allowable Subject Matter
30. Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
31. Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM C WOOD whose telephone number is (571)272-5285. The examiner can normally be reached Monday - Friday, 8:00 am - 4:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chat C Do can be reached at 571-272-3721. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WILLIAM C WOOD/Examiner, Art Unit 2193
/Chat C Do/Supervisory Patent Examiner, Art Unit 2193
Prosecution Insights