Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 05/08/2026 has been entered.
DETAILED ACTION
Claims 1 – 15 and 17 – 21 are pending.
Response to Arguments
Applicant’s arguments, filed 12/12/2025, with respect to the rejection of claim 1 – 20 under 35 U.S.C. 102(a)(1), have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Magnavacca, U.S. Publication 0223/0376230.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 15 and 17 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Piszczek et al., U.S. Patent 9,639,457 (herein Piszczek), in view of Magnavacca, U.S. Publication 0223/0376230 (herein Magnavacca).
Regarding claims 1, 11, and 18, claim 1 as representative, Piszczek teaches: A first storage device, comprising: a first non-volatile memory (figure 3, element 34); and a controller (figure 3, element 42) configured to: receive a plurality of data segments from a compute node via an interface (claim 1 (d)); determine at least one intermediate parity based on performing at least one XOR operation on the plurality of data segments, the at least one intermediate parity being stored in at least one device buffer of the first storage device (claim 1 (g)); the at least one intermediate parity corresponds to one of a plurality of intermediate parities used to determine at least one partial parity of a redundant array of independent disk (RAID) volume (claim 1 (h)); and store the plurality of data segments in at least the first storage device and a second storage device (claim 1 (i)(j)). Piszczek does not explicitly teach: transmit the at least one intermediate parity of the at least one device buffer to at least one parity storage device,
Magnavacca teaches: transmit the at least one intermediate parity of the at least one device buffer to at least one parity storage device (paragraph 0052 “the processing device can move the parity data stored in the temporary storage location to a permanent or non-volatile storage location”).
One of ordinary skill in the art, at the time of the effective filing date of the invention, would find it obvious to combine the teaching of Piszczek: a first storage device, comprising: a first non-volatile memory, and a controller configured to: determine at least one intermediate parity based on performing at least one XOR operation of the plurality of data segments; with the teaching of Magnavacca: transferring parity data from a temporary storage location to a permanent or non-volatile storage location for the purpose of managing memory resources (paragraph 0052). Memory devices are well-known in the art (abstract). Generation of intermediate parity is a well-known design choice in the art (claim 1 (h)). Transferring parity data to permanent or non-volatile storage location is a well-known design choice in the art (paragraph 0052). The Examiner asserts the “a permanent or non-volatile storage location” disclosed by Magnavacca would be understood by one of ordinary skill in the art, at the time of filing, to be a “at least one parity storage device” as claimed by applicant. The examiner asserts a “at least one parity storage device” would be understood by one of ordinary skill in the art, at the time of filing, as a storage device which parity information can be stored. One of ordinary skill in the art would recognize the use of well-known design choice would yield a predictable result.
Regarding claims 2, 12, and 19, claim 2 as representative, Piszczek and Magnavacca teach the limitations of the parent claim. Piszczek additionally teaches: receive an XOR command from the compute node via the interface; and wherein determining the at least one intermediate parity is in response to receiving the XOR command (claim 1 (d)). And in view of the motivation previously stated above, for claim 1, the claim is rejected.
Regarding claims 3, 13, and 20, claim 3 as representative, Piszczek and Magnavacca teach the limitations of the parent claim. Piszczek additionally teaches: performing a first write operation to write a first portion (D1) of the plurality of data segments to the first non-volatile memory of the first storage device (claim 1; column 7, lines 10 – 30); and performing a second write operation to write a second portion (D2) of the plurality of data segments to a second non-volatile memory of the second storage device (claim 1; column 7, lines 10 – 30). And in view of the motivation previously stated above, for claim 1, the claim is rejected.
Regarding claims 4, and 14, claim 4 as representative, Piszczek and Magnavacca teach the limitations of the parent claim. Piszczek additionally teaches: the first storage device is one of a plurality of storage devices of a first data node of a plurality of data nodes of the RAID volume (figure 3, element 42; column 7, lines 10 – 30); and each of the storage devices is a solid-state drive (SSD) in communication with the compute node via the interface (figure 3, element 46A, 34). And in view of the motivation previously stated above, for claim 1, the claim is rejected.
Regarding claims 5, and 15, claim 5 as representative, Piszczek and Magnavacca teach the limitations of the parent claim. Piszczek additionally teaches: the at least one parity storage device corresponds to a second data node of the plurality of data nodes (figure 3; column 7, lines 10 – 30); and the first storage device and the at least one parity storage device operatively coupled via the interface (figure 3, element 36). And in view of the motivation previously stated above, for claim 1, the claim is rejected.
Regarding claim 6, Piszczek and Magnavacca teach the limitations of the parent claim. Piszczek additionally teaches: the plurality of data segments is received according to a direct memory access (DMA) command issued by the compute node (column 12, lines 55 – 56). And in view of the motivation previously stated above, for claim 1, the claim is rejected.
Regarding claims 7, and 17, claim 7 as representative, Piszczek and Magnavacca teach the limitations of the parent claim. Piszczek additionally teaches: the at least one intermediate parity comprises an intermediate partial P parity bit and an intermediate partial Q parity bit of the plurality of data segments (claim 1 (g)(h)(i)). And in view of the motivation previously stated above, for claim 1, the claim is rejected.
Regarding claim 8, Piszczek and Magnavacca teach the limitations of the parent claim. Piszczek additionally teaches: in response to receiving the plurality of data segments, perform a store operation to store the plurality of data segments to one or more controller memory buffers (CMBs) of the controller (figure 3, 50A; element claim 1 (j)); and in response to determining the at least one intermediate parity, store the at least one intermediate parity in the one or more CMBs of the controller (figure 3, 50A; element claim 1 (j)). And in view of the motivation previously stated above, for claim 1, the claim is rejected.
Regarding claim 9, Piszczek and Magnavacca teach the limitations of the parent claim. Piszczek additionally teaches: the at least one device buffer is the one or more CMBs of the controller (figure 3, 50A; element claim 1 (j)); and the transmission of the at least one intermediate parity to the at least one parity storage device comprises transmitting the at least one intermediate parity to one or more remote CMBs of a remote controller of the at least one parity storage device (claim 1; column 7, lines 10 – 30). And in view of the motivation previously stated above, for claim 1, the claim is rejected.
Regarding claim 10, Piszczek and Magnavacca teach the limitations of the parent claim. Piszczek additionally teaches: the at least one intermediate parity is set determined byte-by-byte using the at least XOR operation on the plurality of data segments (claim 1 (g)(h)). And in view of the motivation previously stated above, for claim 1, the claim is rejected.
Allowable Subject Matter
Claim 21 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Closest Prior Art of Record
Bert, U.S. Publication 2023/0333783
Burt teaches: a system component, such as memory sub-system controller, to dynamically generate Redundant Array of Independent Nodes (RAIN) parity information for zone-based memory allocations. The RAIN parity information is generated for a given zone or set of zones on the basis of whether the given zone or set of zones satisfy a zone completeness criterion. The zone completeness criterion can represent a specified size such that when a given zone reaches the specified size, the parity information for that zone is generated.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL F MCMAHON whose telephone number is (571)270-3232. The examiner can normally be reached Monday-Thursday 9am - 5pm EST.
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/Daniel F. McMahon/Primary Examiner, Art Unit 2111
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