DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Application filed June 28, 2024.
Claims 1-20 are pending. Claims 1, 10 and 16 are independent.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55 received on August 6, 2024.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on June 28, 2024. This IDS has been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ayyapureddi (U.S. 2022/0051711).
Regarding independent claim 1, Ayyapureddi discloses a self-refresh method (see pages 2-3, par. 0020) of a semiconductor memory device (Fig. 1), comprising:
receiving a self-refresh entry command (“self-refresh entry command,” see pages 2-3, par. 0020);
performing a self-refresh cycle based on the self-refresh entry command (see pages 2-3, par. 0020);
receiving a self-refresh exit command (“self-refresh exit command,” see pages 2-3, par. 0020);
based on receiving the self-refresh exit command, determining a refresh operation status (“AREF to stop and return to an idle state,” see pages 2-3, par. 0020); and
based on determining that the refresh operation status indicating an idle state (“AREF to stop and return to an idle state,” see pages 2-3, par. 0020), executing a care refresh operation corresponding to row-hammer care (“The RHR state control circuit may provide a set of activations of RHR and IREF responsive to the refresh signal AREF,” see page 6, par. 0053-0054).
Regarding claim 2, Ayyapureddi discloses skipping the care refresh operation based on determining that the refresh operation status indicates a refresh state in which at least one of an active operation, a restore operation, and a precharge operation for the selected memory cell is activated (When a self-refresh entry command is received, the refresh state is not in idle state, therefore self-refresh operation is carried out, see pages 2-3, par. 0020).
Regarding claim 3, Ayyapureddi discloses detecting a row-hammer attack on the semiconductor memory device (see page 1, par. 0009).
Regarding claim 4, Ayyapureddi discloses wherein the care refresh operation is executed based on the row-hammer attack being detected (“The aggressor detector circuit may provide a match address HitXADD,” see page 6, par. 0053) and determining that the refresh operation status indicates the idle state (“The RHR state control circuit may provide a set of activations of RHR and IREF responsive to the refresh signal AREF,” see page 6, par. 0053-0054).
Regarding claim 5, Ayyapureddi discloses based on determining that the refresh operation status indicates the idle state (“The RHR state control circuit may provide a set of activations of RHR and IREF responsive to the refresh signal AREF,” see page 6, par. 0053-0054), determining whether a row-hammer attack is detected (“The aggressor detector circuit may provide a match address HitXADD,” see page 6, par. 0053),
wherein the care refresh operation is skipped based on the row-hammer attack being not detected and determining that the refresh operation status indicates the idle state (If not match address HitXADD is provided, row hammer refresh will not occur, see page 6, par. 0053).
Regarding claim 6, Ayyapureddi discloses wherein the detecting the row-hammer attack comprises:
counting a number of accesses to an aggressor word line (see page 6, par. 0059); and
based on the counted number of accesses reaching a threshold, determining that the row-hammer attack has occurred (see pages 6-7, par. 0059-0060).
Regarding claim 7, Ayyapureddi discloses based on a plurality of self-refresh entry command being received, counting a number of consecutive self-refresh entry commands (For every self-refresh mode command issued to the memory device, signal AREF is activated and the refresh control supplies a refresh row address RXADD based on AREF, see pages 2-3, par. 0020, and the aggressor detector circuit count the number of times that each address XADD is received, see page 6, par. 0059).
Regarding claim 8, Ayyapureddi discloses wherein based on the number of consecutive self-refresh entry commands being less than a reference value, the care refresh is skipped (If not match address HitXADD is provided, row hammer refresh will not occur, see page 6, par. 0053. HitXADD is provided only when the count exceeds a threshold, see pages 6-7, par. 0060).
Regarding claim 9, Ayyapureddi discloses wherein the care refresh operation is performed based on the number of consecutive self-refresh entry command being greater than or equal to the reference value (When HitXADD is provided by the aggressor detector, refresh of the victim rows should occur, see page 6, par. 0053. HitXADD is provided only when the count exceeds a threshold, see pages 6-7, par. 0060).
Regarding independent claim 10, Ayyapureddi discloses a semiconductor memory device (Fig. 1), comprising:
a cell array (Fig. 1: 118) comprising a plurality of dynamic random access memory (DRAM) cells (see page 1, par. 0012);
a command decoder configured to decode commands received by the semiconductor memory device and to generate a self-refresh entry command and a self-refresh exit command (Fig. 1: 106, see also pages 2-3, par. 0020);
a care refresh control circuit (Fig. 1: 116) configured to generate a care refresh control signal (Fig. 5: RHR) for performing a care refresh operation on victim cells based on the self-refresh entry command, the self-refresh exit command corresponding to selected memory cells, and a refresh operation status (see pages 2-3, par. 0020); and
a refresh controller (Fig. 5: 508) configured to perform a self-refresh operation on the selected memory cells and the care refresh operation on the victim cells based on receiving the care refresh control signal (Fig. 5: RHR),
wherein the care refresh control circuit is further configured to generate the care refresh control signal (“The RHR state control circuit may provide a set of activations of RHR and IREF responsive to the refresh signal AREF,” see page 6, par. 0053-0054) based on determining that the refresh operation status indicates an idle state (“AREF to stop and return to an idle state,” see pages 2-3, par. 0020), and to skip the care refresh operation based on determining that the refresh operation status indicates a refresh state (When a self-refresh entry command is received, the refresh state is not in idle state, therefore self-refresh operation is carried out, see pages 2-3, par. 0020).
Regarding claim 11, Ayyapureddi discloses wherein the care refresh control circuit (Fig. 5: 516) comprises:
a status monitor configured to monitor the refresh operation status and generate a status flag (Fig. 5: 536, see also page 6, par. 0053-0054);
a command generator configured to generate a care refresh command according to the self-refresh entry command, the self-refresh exit command, and the status flag (Fig. 5: 532 and 536); and
a care refresh manager configured to generate the care refresh control signal based on whether the care refresh command is activated (Fig. 5: 534).
Regarding claim 12, Ayyapureddi discloses an aggressor word line counter configured to activate the care refresh control signal based on a number of accesses to an aggressor word line (Fig. 5: 532).
Regarding claim 13, Ayyapureddi discloses wherein the status monitor is further configured to determine the refresh operation status using at least one of an active signal, a restore signal, and a precharge signal corresponding to the selected memory cells (Fig. 5: 536, see also page 6, par. 0053-0054).
Regarding claim 14, Ayyapureddi discloses wherein the care refresh control circuit (Fig. 5: 516) comprises:
a status monitor configured to monitor the refresh operation status and generate a status flag (Fig. 5: 536, see also page 6, par. 0053-0054);
a self-refresh counter (Fig. 5: 532) configured to, based on a plurality of self-refresh commands being received, count a number of consecutive self-refresh entry commands and generate a count flag (For every self-refresh mode command issued to the memory device, signal AREF is activated and the refresh control supplies a refresh row address RXADD based on AREF, see pages 2-3, par. 0020, and the aggressor detector circuit count the number of times that each address XADD is received, see page 6, par. 0059),;
a command generator configured to generate a care refresh command according to the self-refresh entry command, the self-refresh exit command, and the status flag (Fig. 5: 532 and 536); and
a care refresh manager configured to generate the care refresh control signal based on whether the care refresh command is activated (Fig. 5: 534).
Regarding claim 15, Ayyapureddi discloses wherein the self-refresh counter is further configured to activate the count flag based on the number of the consecutive self-refresh entry commands being greater than or equal to a reference value When HitXADD is provided by the aggressor detector, refresh of the victim rows should occur, see page 6, par. 0053. HitXADD is provided only when the count exceeds a threshold, see pages 6-7, par. 0060).
Regarding independent claim 16, Ayyapureddi discloses a self-refresh method (see pages 2-3, par. 0020) of a semiconductor memory device (Fig. 1), comprising:
performing a self-refresh cycle comprising a refresh state and an idle state as refresh operation status for the selected memory cells (see pages 2-3, par. 0020);
receiving a self-refresh exit command (“self-refresh exit command,” see pages 2-3, par. 0020);
based on receiving the self-refresh exit command, determining a current refresh operation status (“AREF to stop and return to an idle state,” see pages 2-3, par. 0020); and
executing a care refresh operation for row-hammer care based on the current refresh operation status (“The RHR state control circuit may provide a set of activations of RHR and IREF responsive to the refresh signal AREF,” see page 6, par. 0053-0054).
Regarding claim 17, Ayyapureddi discloses based on determining that the current refresh operation status indicates the refresh state, skipping the care refresh operation (When a self-refresh entry command is received, the refresh state is not in idle state, therefore self-refresh operation is carried out, see pages 2-3, par. 0020).
Regarding claim 18, Ayyapureddi wherein the care refresh operation is executed based on determining that the current refresh operation status indicates the idle state (“AREF to stop and return to an idle state,” see pages 2-3, par. 0020; “The RHR state control circuit may provide a set of activations of RHR and IREF responsive to the refresh signal AREF,” see page 6, par. 0053-0054).
Regarding claim 19, Ayyapureddi discloses detecting a row-hammer attack on the semiconductor memory device (see page 1, par. 0009),
wherein the care refresh operation is executed based on the row-hammer attack being detected (“The aggressor detector circuit may provide a match address HitXADD,” see page 6, par. 0053) and determining that the refresh operation status indicates the idle state (“The RHR state control circuit may provide a set of activations of RHR and IREF responsive to the refresh signal AREF,” see page 6, par. 0053-0054).
Regarding claim 20, Ayyapureddi discloses receiving a plurality of self-refresh entry commands; and based on receiving the plurality of self-refresh entry commands, counting a number of consecutive self-refresh entry commands (For every self-refresh mode command issued to the memory device, signal AREF is activated and the refresh control supplies a refresh row address RXADD based on AREF, see pages 2-3, par. 0020, and the aggressor detector circuit count the number of times that each address XADD is received, see page 6, par. 0059),
wherein based on the number of consecutive self-refresh entry commands being less than a reference value, the care refresh operation is skipped (If not match address HitXADD is provided, row hammer refresh will not occur, see page 6, par. 0053. HitXADD is provided only when the count exceeds a threshold, see pages 6-7, par. 0060).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
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/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825