Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
METHOD OF CONNECTIVITY OF AN OPTOELECTRONIC COMPONENT IN A CAVITY
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-7 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Maeda et al. [US PGPUB 20080023713] (hereinafter Maeda).
Regarding claim 1, Maeda teaches a method for producing an optoelectronic component comprising
- providing a carrier (11, Para 129, Fig. 1),
- arranging a first contact layer (14, Para 135) which has an electrically conductive material on the carrier (Para 136),
- arranging an insulating layer (12, Para 129) which has an electrically insulating material on the carrier (Para 129), wherein the insulating layer has a cavity (Fig. 1), and
- arranging an optoelectronic semiconductor chip (18, Para 129) in the cavity (Fig. 1),
wherein the first contact layer is arranged between the optoelectronic semiconductor chip and the carrier (Fig. 1) and between the insulating layer and the carrier (Fig. 1), and
wherein the first contact layer has at least one interruption, such that the carrier is free of the first contact layer at least in places in a region of the cavity (Fig. 1).
Regarding claim 4, Maeda teaches a method wherein the cavity extends completely through the insulating layer from a top side facing away from the carrier to the carrier (Fig. 1).
Regarding claim 5, Maeda teaches a method wherein the cavity has side walls which are perpendicular to a main extension plane of the carrier (Fig. 1).
Regarding claim 6, Maeda teaches a method further comprising arranging a second contact layer (15, Para 133) at least in places on an underside of the carrier facing away from the insulating layer (Fig. 1),
wherein the second contact layer has an electrically conductive material (Para 133), and
wherein the second contact layer has at least one interruption (Fig. 1), so that the carrier is free of the second contact layer at least in places in the region of the cavity (Fig. 1 –i.e., the second contact layer is not present in the region of the second cavity).
Regarding claim 7, Maeda teaches a method wherein the carrier comprises at least one area in the region of the cavity which is free of the first contact layer, the second contact layer and the optoelectronic semiconductor chip (Fig. 1).
Regarding claim 9, Maeda teaches a method wherein a fourth contact layer (22, Para 136) is electrically connected to the second contact layer through at least one via (16, Para 136) in the insulating layer (Fig. 1).
Claims 1, 2, 6, 8 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. [US PGPUB 20070057364] (hereinafter Wang).
Regarding claim 1, Wang teaches a method for producing an optoelectronic component comprising
- providing a carrier (108, Para 31, Fig. 1A),
- arranging a first contact layer (110, Para 31) which has an electrically conductive material on the carrier (Para 31),
- arranging an insulating layer (111, Para 31) which has an electrically insulating material on the carrier (Para 31), wherein the insulating layer has a cavity (Fig. 1A), and
- arranging an optoelectronic semiconductor chip (LED chip, Para 31) in the cavity (Para 31, Fig. 1A),
wherein the first contact layer is arranged between the optoelectronic semiconductor chip and the carrier and between the insulating layer and the carrier (Fig. 1A), and
wherein the first contact layer has at least one interruption, such that the carrier is free of the first contact layer at least in places in a region of the cavity (Fig. 1A).
Regarding claim 2, Wang teaches a method further comprising arranging a third contact layer (103, Para 31) on a top side of the insulating layer facing away from the carrier (Fig. 1A), wherein the third contact layer has an electrically conductive material (Para 31).
Regarding claim 6, Wang teaches a method further comprising arranging a second contact layer (15, Para 133) at least in places on an underside of the carrier facing away from the insulating layer (Fig. 1),
wherein the second contact layer has an electrically conductive material (Para 133), and
wherein the second contact layer has at least one interruption (Fig. 1), so that the carrier is free of the second contact layer at least in places in the region of the cavity (Fig. 1).
Regarding claim 8, Wang teaches a method wherein the carrier has at least two places in the region of the cavity free of the first contact layer, the second contact layer, and the semiconductor chip (Fig. 1).
Regarding claim 11, Wang teaches a method wherein the first contact layer has at least two interruptions (Fig. 1A).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-8 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. [US PPGUB 20160050771] (hereinafter Yu).
Regarding claim 1, Yu teaches a method for producing an optoelectronic component comprising
- providing a carrier (110/120, Fig. 2),
- arranging a first contact layer (114a of contact 130a, Para 22; where 130a is a stack of 114a and 118a, Fig.1E) which has an electrically conductive material on the carrier (Para 22),
- arranging an insulating layer (142a, Para 25) which has an electrically insulating material on the carrier (Para 125), wherein the insulating layer has a cavity (146a, Para 26), and
- arranging an chip (150, Para 28) in the cavity (Fig. 2),
wherein the first contact layer is arranged between the optoelectronic semiconductor chip and the carrier and between the insulating layer and the carrier (Fig. 2), and
wherein the first contact layer has at least one interruption (Fig. 2; i.e., in view of layer 120), such that the carrier is free of the first contact layer at least in places in a region of the cavity (Fig. 2).
Yu does not specifically disclose that the chip is an optoelectronic semiconductor chip.
It is noted that Yu discloses that various different components (e.g., chips, connectors, optoelectronic components or heat-dissipation components, etc.) may also be disposed in the circuit structure based on demands, so as to increase functionality of the circuit structure (Para 4).
Thus, a person having ordinary skills in the art would find it obvious before the effective filing date of the claimed invention to use an optoelectronic component in the structure of Yu instead of “a chip” to form a light emitting device. The reasoning based on the rationale of relying on teachings, suggestions, or motivation in the prior art that could lead one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention (MPEP 2143.I.G)
Regarding claim 2, Yu teaches a method further comprising arranging a third contact layer (144a, Para 25) on a top side of the insulating layer facing away from the carrier (Fig. 2), wherein the third contact layer has an electrically conductive material (Para 25).
Regarding claim 3, Yu teaches a method wherein the third contact layer (144a, Para 25) completely covers the top side of the insulating layer facing away from the carrier (Fig. 2).
Regarding claim 5, Yu teaches a method wherein the cavity has side walls which are perpendicular to a main extension plane of the carrier (Fig. 2).
Regarding claim 6, Yu teaches a method further comprising arranging a second contact layer (130b, Para 22) at least in places on an underside of the carrier facing away from the insulating layer (Fig. 2),
wherein the second contact layer has an electrically conductive material (Para 22), and
wherein the second contact layer has at least one interruption (Fig. 2), so that the carrier is free of the second contact layer at least in places in the region of the cavity (Fig. 1).
Regarding claim 7, Yu teaches a method wherein the carrier comprises at least one area in the region of the cavity which is free of the first contact layer, the second contact layer and the optoelectronic semiconductor chip (Fig. 2).
Regarding claim 8, Yu teaches a method wherein the carrier has at least two places in the region of the cavity free of the first contact layer, the second contact layer, and the semiconductor chip (Fig. 2).
Regarding claim 10, Yu teaches a method wherein the optoelectronic semiconductor chip is protruded over by the insulating layer in a vertical direction or ends flush therewith (Fig. 2, flush), wherein the vertical direction is perpendicular to a main extension plane of the optoelectronic component (Fig. 2).
Regarding claim 11, Yu teaches a method wherein the first contact layer has at least two interruptions (Fig. 2).
Allowable Subject Matter
Claims 12-16 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 12-16 are allowed because all prior arts of record and related prior arts not of record either singularly or in combination fail to anticipate or render obvious an optoelectronic component, comprising:
- the first contact layer has at least two interruptions, such that the carrier is free of the first contact layer at least in places in a region of the cavity,
- in which the third contact layer completely covers the top side of the insulating layer,
- in which a second contact layer, which has an electrically conductive material, is arranged at least in places on an underside of the carrier facing away from the insulating layer and has at least two interruptions, so that the carrier is free of the second contact layer at least in places in the region of the cavity (as claimed in claim 12), in combination with the rest of claim limitations as claimed and defined by the Applicant.
Conclusion
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/ISMAIL A MUSE/ Primary Examiner, Art Unit 2812
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