DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement(s)
The Information Disclosure Statement(s) filed on November 13, 2025 was considered by the Examiner.
Claim Objections
Claim 14 is objected to because of the following informalities: Claim 14 includes “wherein the package is one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle”. As best understood by the examiner, based on [0174] and Fig 12, the package is part of the listed electronic devices, not the entirety of the device. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20240072032A1 (“Song”) in view of US20240136263A1 (“Wang”).
RE: Claim 1, Song discloses A package (800 in FIG. 8) comprising:
a package interposer (combination of 102, 702 and regions of 800 between 102 and 702, including 106, 406, 780, [0077], [0085]) comprising:
a first metallization portion (102 or alternatively: 702, [0085]);
a second metallization portion (702 or alternatively: 102);
a passive device (106; chiplet 106 is configured as a passive chiplet, [0057]) located between the first metallization portion and the second metallization portion,
wherein the passive device comprises a plurality of bump interconnects (labeled in FIG. 1 for 106: 164 or alternatively: 166, [0035]), and
a first integrated device (104, [0085]) coupled to the package interposer.
Song does not explicitly disclose:
the plurality of bump interconnects comprise:
a first plurality of bump interconnects, where each bump interconnect from the first plurality of bump interconnects comprises a first minimum width; and
a second plurality of bump interconnects, where each bump interconnect from the second plurality of bump interconnects comprises a second minimum width that is greater than the first minimum width.
However, in the same field of endeavor, Wang discloses in FIGs. 2, 3A-3B:
a plurality of bump interconnects (31a, 32a or 31b, 32b, [0039]) comprising:
a first plurality of bump interconnects (32a or 32b; 32a, 32b, include bumps, [0039]), where each bump interconnect from the first plurality of bump interconnects comprises a first minimum width (FIG. 3A shows each 32a comprises a first minimum width; FIG. 3B shows each 32b comprises a first minimum width); and
a second plurality of bump interconnects (31a or 31b; 31a, 31b include solder balls, [0035]; FIG. 2 shows 31a, 31b form bumps and are therefore considered bump interconnects), where each bump interconnect from the second plurality of bump interconnects comprises a second minimum width that is greater than the first minimum width (the amount of solder of the first conductive structures 31 a, 31 b is greater than the amount of solder of the second conductive structures 32 a, 32 b, [0043]; FIGs. 2 and 3A show that as a result of 31a having a greater amount of solder than 32a, each 31a comprises a second minimum width that is greater than the first minimum width of each 32a; FIGs. 2 and 3B show that as a result of 31b having a greater amount of solder than 32b, each 31b comprises a second minimum width that is greater than the first minimum width of each 32b).
Wang further teaches:
Therefore, in the electronic package 2 of the present disclosure, the first electronic module 2 a and the second electronic module 2 b are stacked mainly by the first conductive structures 31 a, the second conductive structures 32 a and the third conductive structures 33 a of different structures, and more solder materials 310, 320 with better stress absorption effect are arranged on a region of the first interlayer L1 that is closer to the periphery, that is, the first conductive structures 31 a with the largest amount of solder, the second conductive structures 32 a with the second largest amount of solder, and the third conductive structures 33 a without solder are sequentially arranged in the first interlayer L1 from outside to inside, so as to effectively disperse the stress and avoid the problem of stress concentration, [0049].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the interconnects 164 and/or the interconnects 166 to have a first plurality of bump interconnects each having a first minimum width, and a second plurality of bump interconnects each having a second minimum width larger than the first minimum width of each of the first plurality of bump interconnects, where the second plurality of bump interconnects have a greater amount of solder than the first plurality of bump interconnects as taught by Wang in order to disperse stress and to avoid the problem of stress concentration as further taught by Wang, [0049].
RE: Claim 2, Song in view of Wang discloses The package of claim 1, wherein at least one bump interconnect from the second plurality of bump interconnects is located in a first corner region of the passive device (FIGs. 3A, 3B Wang show that at least one bump interconnect 31a, 31b is located in a first top right corner region of L1, L2, respectively; Accordingly as modified, at least one bump interconnect from the second plurality of bump interconnects of 164 or 166 is located in a first corner region of the passive device 106 in Song).
RE: Claim 3, Song in view of Wang discloses The package of claim 2, wherein at least one other bump interconnect from the second plurality of bump interconnects is located in a second corner region of the passive device (FIGs. 3A, 3B Wang show that at least one other bump interconnect 31a, 31b is located in a second top left corner region of L1, L2, respectively; Accordingly as modified, at least one other bump interconnect from the second plurality of bump interconnects of 164 or 166 is located in a second corner region of the passive device 106 in Song).
RE: Claim 4, Song in view of Wang discloses The package of claim 1, wherein the second plurality of bump interconnects comprise:
a first bump interconnect located in a first corner region of the passive device (FIGs. 3A, 3B Wang show that a first bump interconnect 31a, 31b is located in a first top right corner region of L1, L2, respectively; Accordingly as modified, a first bump interconnect from the second plurality of bump interconnects of 164 or 166 is located in a first corner region of the passive device 106 in Song);
a second bump interconnect located in a second corner region of the passive device (FIGs. 3A, 3B Wang show that a second bump interconnect 31a, 31b is located in a second top left corner region of L1, L2, respectively; Accordingly as modified, a second bump interconnect from the second plurality of bump interconnects of 164 or 166 is located in a second corner region of the passive device 106 in Song);
a third bump interconnect located in a third corner region of the passive device (FIGs. 3A, 3B Wang show that a third bump interconnect 31a, 31b is located in a third bottom left corner region of L1, L2, respectively; Accordingly as modified, a third bump interconnect from the second plurality of bump interconnects of 164 or 166 is located in a third corner region of the passive device 106 in Song); and
a fourth bump interconnect located in a fourth corner region of the passive device (FIGs. 3A, 3B Wang show that a fourth bump interconnect 31a, 31b is located in a fourth bottom right corner region of L1, L2, respectively; Accordingly as modified, a fourth bump interconnect from the second plurality of bump interconnects of 164 or 166 is located in a fourth corner region of the passive device 106 in Song).
RE: Claim 5, Song in view of Wang discloses The package of claim 1, wherein the plurality of bump interconnects comprise a bump interconnect that includes a post interconnect and/or a solder interconnect (Wang teaches the amount of solder of the first conductive structures 31 a, 31 b is greater than the amount of solder of the second conductive structures 32 a, 32 b, [0043]; Accordingly as modified, the plurality of bump interconnects 164 or 166 in Song comprise solder and are therefore considered solder interconnects).
RE: Claim 6, Song in view of Wang discloses The package of claim 1, wherein the plurality of bump interconnects are located on a front side of the passive device (Song teaches The plurality of trench interconnects 164 are located on a front side (e.g., top side) of the chiplet 106, [0035]).
RE: Claim 7, Song in view of Wang discloses The package of claim 1, wherein the plurality of bump interconnects are located on a back side of the passive device (Song teaches The plurality of trench interconnects 166 are located on a back side (e.g., bottom side) of the chiplet 106, [0035]).
RE: Claim 8, Song in view of Wang discloses The package of claim 1,
wherein the first plurality of bump interconnects include a plurality of inner bump interconnects (FIGs. 3A, 3B Wang show the first plurality of bump interconnects 32a, 32b are inner bump interconnects relative to interconnects 31a, 31b, respectively; Accordingly, as modified, the first plurality of bump interconnects of 164 or 166 in Song include a plurality of inner bump interconnects), and
wherein the second plurality of bump interconnects include a plurality of periphery bump interconnects located along one or more edges of the passive device (Wang teaches in FIG. 3A, the first conductive structures 31 a of the first interlayer L1 are arranged in two circles along the edge of the rectangular region; and as shown in FIG. 3B, the first conductive structures 31 b of the second interlayer L2 are arranged in three circles along the edge of the rectangular region, [0037]; Accordingly as modified, the second plurality of bump interconnects of 164 or 166 include a plurality of periphery bump interconnects located along one or more edges of the passive device 106 in Song).
RE: Claim 9, Song in view of Wang discloses The package of claim 1,
wherein the package interposer further comprises a first encapsulation layer (In Song FIG. 8: 708, [0085]) located between the first metallization portion and the second metallization portion, and
wherein the first encapsulation layer at least partially encapsulates the passive device (Song FIG. 8 shows 708 at least partially encapsulating passive device 106).
RE: Claim 10, Song in view of Wang discloses The package of claim 1,
wherein the passive device further comprises a plurality of front side bump interconnects (164; Song teaches The plurality of trench interconnects 164 are located on a front side (e.g., top side) of the chiplet 106, [0035]),
wherein the plurality of bump interconnects (166, [0035]) comprise a plurality of back side bump interconnects (166; Song teaches The plurality of trench interconnects 166 are located on a back side (e.g., bottom side) of the chiplet 106, [0035]),
wherein the passive device is coupled to the first metallization portion (102) through the plurality of front side bump interconnects (164 are shown on the top/front side of 106 in Song FIG. 8 though 164 are not labeled therein; 164 are labeled and shown on the top/front of 106 in FIG. 1; Accordingly Song FIG. 8 shows the passive device 106 is coupled to the first metallization portion 102 through the plurality of front side bump interconnects 164), and
wherein the passive device is coupled to the second metallization (702) portion through the plurality of back side bump interconnects (166 are shown on the bottom/back side of 106 in Song FIG. 8 though 166 are not labeled therein; 166 are labeled and shown on the bottom/back of 106 in FIG. 1; Accordingly Song FIG. 8 shows the passive device 106 is coupled to the second metallization portion 702 through the plurality of back side bump interconnects 166).
RE: Claim 11, Song in view of Wang discloses The package of claim 1,
wherein the passive device further comprises a plurality of front side bump interconnects (164; Song teaches The plurality of trench interconnects 164 are located on a front side (e.g., top side) of the chiplet 106, [0035]),
wherein the plurality of bump interconnects (166, [0035]) comprise a plurality of back side bump interconnects (166; Song teaches The plurality of trench interconnects 166 are located on a back side (e.g., bottom side) of the chiplet 106, [0035]),
wherein the passive device is coupled to the second metallization portion (102) through the plurality of front side bump interconnects (164 are shown on the top/front side of 106 in Song FIG. 8 though 164 is not labeled therein; 164 are labeled and shown on the top/front of 106 in FIG. 1; Accordingly Song FIG. 8 shows the passive device 106 is coupled to the second metallization portion 102 through the plurality of front side bump interconnects 164), and
wherein the passive device is coupled to the first metallization portion (702) through the plurality of back side bump interconnects (166 are shown on the bottom/back side of 106 in Song FIG. 8 though 166 is not labeled therein; 166 are labeled and shown on the bottom/back of 106 in FIG. 1; Accordingly Song FIG. 8 shows the passive device 106 is coupled to the first metallization portion 702 through the plurality of back side bump interconnects 166).
RE: Claim 12, Song in view of Wang discloses The package of claim 1, wherein the passive device is configured to be electrically coupled to the first integrated device (Song teaches integrated device 104 is configured to be electrically coupled to the chiplet 106, [0062]).
RE: Claim 13, Song in view of Wang discloses The package of claim 1, further comprising a second integrated device (In Song FIG. 8: 404, [0085]) coupled to the package interposer,
wherein the package interposer further comprises a bridge (In Song FIG. 8: 505, [0085]) located between the first metallization portion and the second metallization portion.
RE: Claim 14, Song in view of Wang discloses The package of claim 1, wherein the package is one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle (Song teaches automotive vehicle 1910 includes device 1900, [0218]; The device 1900 may be, for example, any of the devices and/or integrated circuit (IC) packages described herein, [0218]; As 800 is an IC package, [0085], Song teaches that 800 is a device 1900 in an automotive vehicle 1910).
RE: Claim 15, Song discloses A package (800 in FIG. 8) comprising:
a substrate (709, [0079]); and
a passive device (106; chiplet 106 is configured as a passive chiplet, [0057]) comprising:
a die substrate (160 labeled in FIG. 1 for 106, [0035]);
a plurality of trench capacitors (167 labeled in FIG. 1 for 106, [0035]) located at least partially in the die substrate; and
a plurality of bump interconnects (labeled in FIG. 1 for 106: 166, [0035]).
Song does not explicitly disclose:
the plurality of bump interconnects comprise:
a first plurality of bump interconnects, where each bump interconnect from the first plurality of bump interconnects comprises a first minimum width; and
a second plurality of bump interconnects, where each bump interconnect from the second plurality of bump interconnects comprises a second minimum width that is greater than the first minimum width,
wherein the passive device is coupled to the substrate through the first plurality of bump interconnects and the second plurality of bump interconnects.
However, in the same field of endeavor, Wang discloses in FIGs. 2, 3A-3B:
a plurality of bump interconnects (31b, 32b, [0039]) comprising:
a first plurality of bump interconnects (32b; 32b includes bumps, [0039]), where each bump interconnect from the first plurality of bump interconnects comprises a first minimum width (FIG. 3B shows each 32b comprises a first minimum width); and
a second plurality of bump interconnects (31b; 31b includes solder balls, [0035]; FIG. 2 shows 31b form bumps and are therefore considered bump interconnects), where each bump interconnect from the second plurality of bump interconnects comprises a second minimum width that is greater than the first minimum width (the amount of solder of the first conductive structures 31 a, 31 b is greater than the amount of solder of the second conductive structures 32 a, 32 b, [0043]; FIGs. 2 and 3B show that as a result of 31b having a greater amount of solder than 32b, each 31b comprises a second minimum width that is greater than the first minimum width of each 32b);
wherein a passive device (2a or 21; 2a includes electronic element 21, [0025]; 21 is a passive element, [0027]; Accordingly, Wang teaches 2a is a passive device) is coupled to a substrate (9, [0057]) through the first plurality of bump interconnects and the second plurality of bump interconnects (FIG. 2 shows 2a and 21 are coupled to substrate 9 through 31b, 32b).
Wang further teaches:
Therefore, in the electronic package 2 of the present disclosure, the first electronic module 2 a and the second electronic module 2 b are stacked mainly by the first conductive structures 31 a, the second conductive structures 32 a and the third conductive structures 33 a of different structures, and more solder materials 310, 320 with better stress absorption effect are arranged on a region of the first interlayer L1 that is closer to the periphery, that is, the first conductive structures 31 a with the largest amount of solder, the second conductive structures 32 a with the second largest amount of solder, and the third conductive structures 33 a without solder are sequentially arranged in the first interlayer L1 from outside to inside, so as to effectively disperse the stress and avoid the problem of stress concentration, [0049].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the interconnects 166 to have a first plurality of bump interconnects each having a first minimum width, and a second plurality of bump interconnects each having a second minimum width larger than the first minimum width of each of the first plurality of bump interconnects, where the second plurality of bump interconnects have a greater amount of solder than the first plurality of bump interconnects as taught by Wang in order to disperse stress and to avoid the problem of stress concentration as further taught by Wang, [0049].
RE: Claim 16, Song in view of Wang discloses The passive device of claim 15, wherein at least one bump interconnect from the second plurality of bump interconnects is located in a first corner region of the passive device (FIG. 3B Wang show that at least one bump interconnect 31b is located in a first top right corner region of L2; Accordingly as modified, at least one bump interconnect from the second plurality of bump interconnects of 166 is located in a first corner region of the passive device 106 in Song).
RE: Claim 17, Song in view of Wang discloses The passive device of claim 16, wherein at least one other bump interconnect from the second plurality of bump interconnects is located in a second corner region of the passive device (FIG. 3B Wang show that at least one other bump interconnect 31b is located in a second top left corner region of L2; Accordingly as modified, at least one other bump interconnect from the second plurality of bump interconnects of 166 is located in a second corner region of the passive device 106 in Song).
RE: Claim 18, Song in view of Wang discloses The passive device of claim 15, wherein the second plurality of bump interconnects comprise:
a first bump interconnect located in a first corner region of the passive device (FIG. 3B Wang shows that a first bump interconnect 31b is located in a first top right corner region of L2; Accordingly as modified, a first bump interconnect from the second plurality of bump interconnects of 166 is located in a first corner region of the passive device 106 in Song);
a second bump interconnect located in a second corner region of the passive device (FIG. 3B Wang shows that a second bump interconnect 31b is located in a second top left corner region of L2; Accordingly as modified, a second bump interconnect from the second plurality of bump interconnects of 166 is located in a second corner region of the passive device 106 in Song);
a third bump interconnect located in a third corner region of the passive device (FIG. 3B Wang shows that a third bump interconnect 31b is located in a third bottom left corner region of L2; Accordingly as modified, a third bump interconnect from the second plurality of bump interconnects of 166 is located in a third corner region of the passive device 106 in Song); and
a fourth bump interconnect located in a fourth corner region of the passive device (FIG. 3B Wang shows that a fourth bump interconnect 31b is located in a fourth bottom right corner region of L2; Accordingly as modified, a fourth bump interconnect from the second plurality of bump interconnects of 166 is located in a fourth corner region of the passive device 106 in Song).
RE: Claim 19, Song discloses A passive device (106 in FIG. 8; chiplet 106 is configured as a passive chiplet, [0057], [0035]) comprising:
a die substrate (160 labeled in FIG. 1 for 106, [0035]);
a plurality of trench capacitors (167 labeled in FIG. 1 for 106, [0035]) located at least partially in the die substrate; and
a plurality of bump interconnects (labeled in FIG. 1 for 106: 166, [0035]).
Song does not explicitly disclose:
the plurality of bump interconnects comprise:
a first plurality of bump interconnects, where each bump interconnect from the first plurality of bump interconnects comprises a first minimum width; and
a second plurality of bump interconnects, where each bump interconnect from the second plurality of bump interconnects comprises a second minimum width that is greater than the first minimum width.
However, in the same field of endeavor, Wang discloses in FIGs. 2, 3A-3B:
a plurality of bump interconnects (31b, 32b, [0039]) comprising:
a first plurality of bump interconnects (32b; 32b includes bumps, [0039]), where each bump interconnect from the first plurality of bump interconnects comprises a first minimum width (FIG. 3B shows each 32b comprises a first minimum width); and
a second plurality of bump interconnects (31b; 31b includes solder balls, [0035]; FIG. 2 shows 31b form bumps and are therefore considered bump interconnects), where each bump interconnect from the second plurality of bump interconnects comprises a second minimum width that is greater than the first minimum width (the amount of solder of the first conductive structures 31 a, 31 b is greater than the amount of solder of the second conductive structures 32 a, 32 b, [0043]; FIGs. 2 and 3B show that as a result of 31b having a greater amount of solder than 32b, each 31b comprises a second minimum width that is greater than the first minimum width of each 32b).
Wang further teaches:
Therefore, in the electronic package 2 of the present disclosure, the first electronic module 2 a and the second electronic module 2 b are stacked mainly by the first conductive structures 31 a, the second conductive structures 32 a and the third conductive structures 33 a of different structures, and more solder materials 310, 320 with better stress absorption effect are arranged on a region of the first interlayer L1 that is closer to the periphery, that is, the first conductive structures 31 a with the largest amount of solder, the second conductive structures 32 a with the second largest amount of solder, and the third conductive structures 33 a without solder are sequentially arranged in the first interlayer L1 from outside to inside, so as to effectively disperse the stress and avoid the problem of stress concentration, [0049].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the interconnects 166 to have a first plurality of bump interconnects each having a first minimum width, and a second plurality of bump interconnects each having a second minimum width larger than the first minimum width of each of the first plurality of bump interconnects, where the second plurality of bump interconnects have a greater amount of solder than the first plurality of bump interconnects as taught by Wang in order to disperse stress and to avoid the problem of stress concentration as further taught by Wang, [0049].
RE: Claim 20, Song in view of Wang discloses The passive device of claim 19, wherein at least one bump interconnect from the second plurality of bump interconnects is located in a first corner region of the passive device (FIG. 3B Wang show that at least one bump interconnect 31b is located in a first top right corner region of L2; Accordingly as modified, at least one bump interconnect from the second plurality of bump interconnects of 166 is located in a first corner region of the passive device 106 in Song).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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