DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US publication 2011/0297949 A1), hereinafter referred to as Lee949, in view of Okabe (US publication 2012/0146037 A1), hereinafter referred to as Okabe037.
Regarding claim 1, Lee949 teaches a method of manufacturing a display device (fig. 1a-1h and related text), the method comprising: forming a buffer layer (110, [0053]) on a substrate (100, [0053]) on which a first region (a portion of region “b”, fig. 1a) and a second region ( apportion of region “a”, fig. 1a) spaced from each other are defined; partially etching the first region of the buffer layer ([0060], fig. 1c); forming an amorphous silicon layer (120a, [0063-0064]) on the buffer layer (fig. 1c); crystallizing the amorphous silicon layer to form a polycrystalline silicon layer ([0065-0070]); etching all regions of the polycrystalline silicon layer except for the first region and the second region to form a first polycrystalline silicon pattern (121, [0069]) and a second polycrystalline silicon pattern (120) in the first region and the second region (fig. 1d), respectively; forming a first gate insulating layer (130, [0072], fig. 1e) on the first polycrystalline silicon pattern and the second polycrystalline silicon pattern (fig. 1e); and forming a first gate electrode (141, [0074]) and a second gate electrode (140) that overlap the first polycrystalline silicon pattern and the second polycrystalline silicon pattern (fig. 1e), respectively, on the first gate insulating layer (fig. 1e).
Lee949 does not explicitly teach polishing the amorphous silicon layer.
Okabe037 teaches polishing the amorphous silicon layer ([0067]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to combine the teachings of Lee949 with that of Okabe037 so that polishing the amorphous silicon layer to form an amorphous silicon layer of a desire thickness.
Regarding claim 2, Lee949 and Okabe037 disclose all the limitations of claim 1 as discussed above on which this claim depends.
Lee949 and Okabe037 do not explicitly teach wherein the polishing of the amorphous silicon layer comprises polishing the amorphous silicon layer to a thickness greater than 0 and less than about 60 Å. However, it is well-known in the art that a width/thickness of a semiconducting layer depends on a process technology, overall size of the device, and is a result-effective variable as electrical properties (conductivity, current, resistance, doping, withstanding breakdown, etc.) depend on the width/thickness of a semiconducting layer. So, a width/thickness of a semiconducting layer is a parameter that one must consider and decide upon and is something that can be optimized through routine experimentation.
Furthermore, it has been held where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. (MPEP §2144.05 II/III).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the teachings of Lee949 and Okabe037 so that wherein the polishing of the amorphous silicon layer comprises polishing the amorphous silicon layer to a thickness greater than 0 and less than about 60 Å or the purpose of optimizing device performance and overall size of the device.
Regarding claim 3, Lee949 and Okabe037 disclose all the limitations of claim 1 as discussed above on which this claim depends.
Lee949 and Okabe037 do not explicitly teach wherein the forming of the amorphous silicon layer comprises forming the amorphous silicon layer to a thickness of about 300 Å to about 500 Å. However, it is well-known in the art that a width/thickness of a semiconducting layer depends on a process technology, overall size of the device, and is a result-effective variable as electrical properties (conductivity, current, resistance, doping, withstanding breakdown, etc.) depend on the width/thickness of a semiconducting layer. So, a width/thickness of a semiconducting layer is a parameter that one must consider and decide upon and is something that can be optimized through routine experimentation.
Furthermore, it has been held where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. (MPEP §2144.05 II/III).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the teachings of Lee949 and Okabe037 so that wherein the forming of the amorphous silicon layer comprises forming the amorphous silicon layer to a thickness of about 300 Å to about 500 Å or the purpose of optimizing device performance and overall size of the device.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable Lee949 in view of Okabe037, as applied to claim 1 above, and further in view of Ikeda et al. (US publication 2003/0139027 A1), hereinafter referred to as Ikeda027.
Regarding claim 4, Lee949 and Okabe037 teach all the limitations of claim 1 as discussed above on which this claim depends.
Lee949 and Okabe037 do not explicitly teach further comprising washing the amorphous silicon layer with hydrofluoric acid after the polishing of the amorphous silicon layer and before the crystallizing of the amorphous silicon layer.
Ikeda027 teaches further comprising washing the amorphous silicon layer with hydrofluoric acid after the polishing of the amorphous silicon layer and before the crystallizing of the amorphous silicon layer ([0117-0118]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to combine the teachings of Lee949 and Okabe037 with that of Ikeda027 so that further comprising washing the amorphous silicon layer with hydrofluoric acid after the polishing of the amorphous silicon layer and before the crystallizing of the amorphous silicon layer to remove impurities.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable Lee949 in view of Okabe037, as applied to claim 1 above, and further in view of Chan et al. (US publication 2007/0284584 A1), hereinafter referred to as Chan584.
Regarding claim 5, Lee949 and Okabe037 teach all the limitations of claim 1 as discussed above on which this claim depends.
Lee949 and Okabe037 do not explicitly teach wherein the crystallizing of the amorphous silicon layer comprises irradiating the amorphous silicon layer by a laser having a constant energy density.
Chan584 teaches wherein the crystallizing of the amorphous silicon layer comprises irradiating the amorphous silicon layer by a laser having a constant energy density ([0025]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to combine the teachings of Lee949 and Okabe037 with that of Chan584 so that wherein the crystallizing of the amorphous silicon layer comprises irradiating the amorphous silicon layer by a laser having a constant energy density so that a well driving current distribution among the driving TFTs is obtained, and OLED elements can emit light uniformly ([0010]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mohammed R Alam whose telephone number is 469-295-9205 and can normally be reached between 8:00am-6:00pm (M-F) or by e-mail via Mohammed.Alam1@uspto.gov.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOHAMMED R ALAM/Primary Examiner, Art Unit 2897
Prosecution Insights