DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Claims 1-20 are pending and have been examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1, 4, 7, and 9-14 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 20140203376 A1 – hereinafter Xie) in view of Cai et al. (US 20130309868 A1 – hereinafter Cai) and Wang et al. (US 20220059685 A1 – hereinafter Wang).
Regarding independent claim 1, Xie teaches:
A method comprising:
forming fins (58 – Fig. 15 – [0017] – “plurality of fins 58”) over a substrate (52
– Fig. 15 – [0017] – “semiconductor substrate 52”);
forming a gate ([0023] – “gate stack 88 overlying fins 58” – this contains a gate,
hereinafter ‘GA’) over the fins (58 – Fig. 15 shows this), wherein a sidewall spacer ([0024] – “the formation of a silicon nitride spacer on the sidewalls of the gate stack, as is known in the art”) is laterally adjacent to the gate (GA);
removing an upper portion of the sidewall spacer;
forming a cavity (74 – Fig. 14A – [0038] – “recesses 74 are formed”) by removing a selected segment of the gate (60 – Fig. 11A – [0036] – “etching results in the removal of the portions of metal gate stack 60 exposed through opening 70”) and removing a selected fin (24’ – Fig. 13A – [0038] – “Protruding fins 24′ (FIG. 13A) and the underlying semiconductor strips 24 are then etched”) located under the selected segment; and
forming an insulation feature (76 – Fig. 17B – [0040] – “formation of dielectric isolation region 76 may include depositing a dielectric material into openings 70, 72, and 74” – this is an insulation feature) in the cavity (74).
Xie does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Cai teaches
removing an upper portion (28 – Fig. 3 – [0032] – “the upper portion 28 of the sidewall spacers 24 is removed with an appropriate etching technique”) of the sidewall spacer (24 – Fig. 5 – [0032] – “the sidewall spacers 24”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the upper portion of the sidewall spacer structure as taught by Cai into Xie.
An ordinary artisan would have been motivated to use the known technique of Cai in the manner set forth above to produce the predictable results [0007] – “to provide methods of forming integrated circuits in which recesses are formed in a dielectric layer using a sacrificial mandrel and sidewall spacers adjacent to sidewalls thereof while alleviating the re-entrant profile of the recesses. Further, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.”
Xie and Cai do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Wang teaches
forming a cavity (74 – Fig. 14A – [0038] – “recesses 74 are formed”) by removing a selected segment of the gate (60 – Fig. 11A – [0036] – “etching results in the removal of the portions of metal gate stack 60 exposed through opening 70”) and removing a selected fin (24’ – Fig. 13A – [0038] – “Protruding fins 24′ (FIG. 13A) and the underlying semiconductor strips 24 are then etched”) located under the selected segment; and
forming an insulation feature (76 – Fig. 17B – [0040] – “formation of dielectric isolation region 76 may include depositing a dielectric material into openings 70, 72, and 74” – this is an insulation feature) in the cavity (74).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the cavity and insulation structure as taught by Wang into Xie and Cai.
An ordinary artisan would have been motivated to use the known technique of Wang in the manner set forth above to produce the predictable results of [0003] – “scaling down has also increased the complexity of processing and manufacturing ICs, and for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, Fin Field-Effect Transistors (FinFETs) have been introduced to replace planar transistors. The structures of FinFETs and methods of fabricating FinFETs are being developed.”
Regarding claim 4, Xie as modified by Cai and Wang, teaches claim 1 from which claim 4 depends. Xie and Wang do not expressly disclose the limitations of claim 4.
However, in an analogous art, Cai teaches
wherein removing the upper portion (28) of the sidewall spacer (24)
comprises removing all of the sidewall spacer (28 – Fig. 5 shows all of the sidewall spacer in the opening removed).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the sidewall spacer structure as taught by Cai into Xie and Wang.
An ordinary artisan would have been motivated to use the known technique of Cai in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 7, Xie as modified by Cai and Wang, teaches claim 1 from which claim 7 depends. Xie further teaches
wherein the gate (GA) is a metal gate ([0023] – “layer of gate electrode
material 92 such as polycrystalline silicon, amorphous silicon, or a metal is deposited”).
Regarding independent claim 9, Xie teaches:
A method for fabricating a semiconductor device (10 – Fig. 1 – {[0004]
– “FinFET IC 10 “}, {[0003] – “a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device”}), the method comprising:
forming fins (58 – Fig. 15 – [0017] – “plurality of fins 58”) over a substrate (52
– Fig. 15 – [0017] – “semiconductor substrate 52”);
forming a gate ([0023] – “gate stack 88 overlying fins 58” – this contains a gate,
hereinafter ‘GA’) over the fins (58 – Fig. 15 shows this);
forming source/drain features in the fin adjacent to the gate;
forming an interlayer dielectric (ILD) structure over the source/drain feature, wherein the ILD structures comprise silicon oxide;
removing a region including a portion of the fin and a portion of the gate to form an opening;
forming an insulation feature in the opening; and
performing a process to etch a selected ILD structure to an underlying source/drain feature, wherein, during the process, an exposed surface of the semiconductor device (10) at and adjacent to the insulation feature is free of silicon oxide.
Xie does not expressly disclose the other limitations of claim 9.
However, in an analogous art, Cai teaches
an exposed surface of the semiconductor device at and adjacent to the insulation feature is free of silicon oxide ([0036] – “Alternatively, when the sidewall spacers 24 include either a silicon nitride or a silicon oxide, and the first region 20 includes a-C, a dry, O.sub.2-based ashing process may be used to selectively remove the first region 20” – Fig. 5 shows all of the sidewall spacer in the opening removed – the sidewall spacer is silicon oxide and is removed).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the structure free of silicon oxide as taught by Cai into Xie.
An ordinary artisan would have been motivated to use the known technique of Cai in the manner set forth above to produce the predictable results of [0036] – “a dry, O.sub.2-based ashing process may be used.”
Xie and Cai do not expressly disclose the other limitations of claim 9.
However, in an analogous art, Wang teaches
forming source/drain (42 – Fig. 11C – [0035] – “source/drain regions 42
between gate stacks 60”) features in the fin (24’ – [0014] – “form protruding fins 24′”) adjacent to the gate (60 – Fig. 11A – [0036] – “etching results in the removal of the portions of metal gate stack 60 exposed through opening 70”);
forming an interlayer dielectric (ILD) structure (48 – Fig. 11C – [0023] –
“Inter-Layer Dielectric (ILD) 48”) over the source/drain feature (42 – Fig. 11C shows this), wherein the ILD (48) structures comprise silicon oxide ([0023] – “ILD 48 may also be formed of an oxygen-containing dielectric material, which may be a silicon-oxide based oxide”);
removing a region including a portion of the fin (24’ – Fig. 13A – [0038] – “Protruding fins 24′ (FIG. 13A) and the underlying semiconductor strips 24 are then etched”) and a portion of the gate (60 – Fig. 11A – [0036] – “etching results in the removal of the portions of metal gate stack 60 exposed through opening 70”) to form an opening (74 – Fig. 14A – [0038] – “recesses 74 are formed”);
forming an insulation feature (76 – Fig. 17B – [0040] – “formation of dielectric isolation region 76 may include depositing a dielectric material into openings 70, 72, and 74” – this is an insulation feature) in the opening (74); and
performing a process to etch a selected ILD structure (48) to an underlying source/drain feature (42 – Fig. 11C shows this), wherein, during the process, an exposed surface of the semiconductor device at and adjacent to the insulation feature (76) is free of silicon oxide.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the source/drain and insulation structure as taught by Wang into Xie and Cai.
An ordinary artisan would have been motivated to use the known technique of Wang in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 10, Xie as modified by Cai and Wang, teaches claim 9 from which claim 10 depends. Xie further teaches
forming a sidewall spacer ([0024] – “the formation of a silicon nitride
spacer on the sidewalls of the gate stack, as is known in the art” – hereinafter ‘SPA’), wherein the sidewall spacer (SPA) is directly adjacent to the gate (GA); and
while removing the region including the portion of the fin and the portion of the gate to form the opening, removing at least an upper portion of a portion of the sidewall spacer within the region.
Xie does not expressly disclose the other limitations of claim 10.
However, in an analogous art, Cai teaches
removing at least an upper portion (28 – Fig. 3 – [0032] – “the upper portion 28 of the sidewall spacers 24 is removed with an appropriate etching technique”) of a portion of the sidewall spacer (24 – Fig. 5 – [0032] – “the sidewall spacers 24”) within the region.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the sidewall spacer structure as taught by Cai into Xie.
An ordinary artisan would have been motivated to use the known technique of Cai in the manner set forth above to produce the predictable results as stated above in claim 1.
Xie and Cai do not expressly disclose the other limitations of claim 10.
However, in an analogous art, Wang teaches
while removing the region including the portion of the fin and the portion of the gate (60) to form the opening (74).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the cavity structure as taught by Wang into Xie and Cai.
An ordinary artisan would have been motivated to use the known technique of Wang in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 11, Xie as modified by Cai and Wang, teaches claim 10 from which claim 11 depends. Xie and Wang do not expressly disclose the limitations of claim 11.
However, in an analogous art, Cai teaches
comprising removing all of the sidewall spacer (28 – Fig. 5 shows all of the
sidewall spacer in the opening removed) within the region.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the sidewall spacer structure as taught by Cai into Xie and Wang.
An ordinary artisan would have been motivated to use the known technique of Cai in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 12, Xie as modified by Cai and Wang, teaches claim 9 from which claim 12 depends. Xie and Cai do not expressly disclose the limitations of claim 12.
However, in an analogous art, Wang teaches
wherein the process to etch ([0033] – “formation of isolation regions 66 may
include etching ILD 48, CESL 46”) the selected ILD structure (48) does not etch (46 – [0023] – “formation of Contact Etch Stop Layer (CESL) 46 and Inter-Layer Dielectric (ILD) 48” – this is interpreted that element 48 is not etched) an interface of the insulation feature (76).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the etching process as taught by Wang into Xie and Cai.
An ordinary artisan would have been motivated to use the known technique of Wang in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 13, Xie as modified by Cai and Wang, teaches claim 9 from which claim 13 depends. Xie further teaches
wherein the gate (GA) is a metal gate ([0023] – “layer of gate electrode
material 92 such as polycrystalline silicon, amorphous silicon, or a metal is deposited”).
Regarding claim 14, Xie as modified by Cai and Wang, teaches claim 9 from which claim 14 depends. Xie and Cai do not expressly disclose the limitations of claim 14.
However, in an analogous art, Wang teaches
wherein the gate (60) is a sacrificial gate ([0036] – “etching results in the removal of the portions of metal gate stack 60 exposed through opening 70” – this is interpreted as a sacrificial gate as it is removed, hereinafter ‘SACG’).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the gate structure as taught by Wang into Xie and Cai.
An ordinary artisan would have been motivated to use the known technique of Wang in the manner set forth above to produce the predictable results as stated above in claim 1.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Cai, Wang, and Smith (US 20230378170 A1).
Regarding claim 2, Xie as modified by Cai and Wang, teaches claim 1 from which claim 2 depends. Xie and Cai do not expressly disclose the limitations of claim 2.
However, in an analogous art, Wang teaches
wherein an interlayer dielectric (ILD) structure (48 – Fig. 17B – [0023] –
“Inter-Layer Dielectric (ILD) 48”) is adjacent to the insulation feature (76), and wherein the method further comprises etching the ILD structure and forming a conductive interconnect to a source/drain feature adjacent to the insulation feature (76).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the ILD and insulation structure as taught by Wang into Xie and Cai.
An ordinary artisan would have been motivated to use the known technique of Wang in the manner set forth above to produce the predictable results as stated above in claim 1.
Xie, Cai, and Wang do not expressly disclose the limitations of claim 2.
However, in an analogous art, Smith teaches
wherein the method further comprises etching the ILD structure ([0137] – “power rails 241a and 241b need to connect to source and drain contacts (also referred to as source and drain structures or S/D structures) 213a and 213b of a CMOS device, and this can be accomplished through multiple techniques such as, but not limited to, (a) extending the metal interconnect down past the shallow trench isolation (STI) 206 to make direct contact to the buried power rails, (b) incorporation of vias 231a and 231b which will extend down from metal interconnects 219a and 219b down past the STI 206 to make direct contact to the power rails 241a and 241b” – this is interpreted as etching to make the downward connection) and forming a conductive interconnect ([0137] – “the metal interconnect”) to a source/drain (213a and 213b – Fig. – 2A – [0137] – “source and drain contacts (also referred to as source and drain structures or S/D structures) 213a and 213b”) feature.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the ILD and interconnect structure as taught by Smith into Xie, Cai, and Wang.
An ordinary artisan would have been motivated to use the known technique of Smith in the manner set forth above to produce the predictable results of [0137] – “a way where the power rails connect upward to either the contact directly or to an interconnect metal which is in contact with the source and drain contacts.”
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Cai, Wang, and Huang (US 20240371857 A1).
Regarding claim 3, Xie as modified by Cai and Wang, teaches claim 1 from which claim 3 depends. Xie and Cai do not expressly disclose the limitations of claim 3.
However, in an analogous art, Wang teaches
forming a source/drain feature (42 – Fig. 11C – [0035] – “source/drain regions
42 between gate stacks 60”) adjacent to the gate (60);
forming an interlayer dielectric (ILD) structure (48 – Fig. 11C – [0023] –
“Inter-Layer Dielectric (ILD) 48”) over the source/drain feature (42 – Fig. 11C shows this), wherein the ILD structure (48) and the sidewall spacer ({38 – fig. 11C – [0026] – “the sidewalls of gate spacers 38”}, {[0018] – “gate spacers 38 are formed of a dielectric material such as silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, silicon oxy carbo-nitride, or the like”}) are formed from a same material ([0030] – “material of hard masks 62 may be the same as or different from some of CESL 46, ILD 48, and/or gate spacers 38” – this is interpreted that elements 48 and 38 are of the same material);
etching the ILD structure and forming a conductive interconnect to the source/drain feature adjacent to the insulation feature,
wherein, if the sidewall spacer (38) is present when etching the ILD structure (48), the insulation feature (68 – Fig. 12B – [0035] – “patterned etching mask 68 is formed over the structure”) covers the sidewall spacer (38) to avoid etching of the sidewall spacer (38).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the source/drain and ILD structure as taught by Wang into Xie and Cai.
An ordinary artisan would have been motivated to use the known technique of Wang in the manner set forth above to produce the predictable results as stated above in claim 1.
Xie, Cai, and Wang do not expressly disclose the other limitations of claim 3.
However, in an analogous art, Huang teaches
etching the ILD structure (123’ – Fig. 25 – [0058] – “interlayer-dielectric (ILD) layer 123′’) and forming a conductive interconnect (137 – Fig. 25 – [0058] – “interconnect structure 137 disposed over the ILD layer 123′”) to the source/drain (121a, 121b – Fig. 25 – [0054] – “source/drain (S/D) regions 121a, 121b”) feature adjacent to the insulation feature (105b – Fig. 25 – [0057] – “the isolation structures 105b”),
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the ILD and interconnect structure as taught by Huang into Xie, Cai, and Wang.
An ordinary artisan would have been motivated to use the known technique of Huang in the manner set forth above to produce the predictable results of [0018] – “a gate electrode of the transistor and a resistor electrode of the resistor are formed in a semiconductor substrate by the same process steps. Therefore, the resistor may have high sheet resistance without using additional masks or process steps. As a result, the associated costs may be reduced, and the performance of the semiconductor device structure may be improved.”
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Cai, Wang, and Lee et al. (US 20070224756 A1 – hereinafter Lee).
Regarding claim 5, Xie as modified by Cai and Wang, teaches claim 1 from which claim 5 depends. Xie and Wang do not expressly disclose the limitations of claim 5.
However, in an analogous art, Cai teaches
the upper portion (28) of the sidewall spacer.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the sidewall spacer structure as taught by Cai into Xie and Wang.
An ordinary artisan would have been motivated to use the known technique of Cai in the manner set forth above to produce the predictable results as stated above in claim 1.
Xie, Cai, and Wang do not expressly disclose the other limitations of claim 5.
However, in an analogous art, Lee teaches
wherein removing the upper portion of the sidewall spacer (42 – Fig. 13 –
[0027] – “spacer 42 at sidewall”) is performed after removing ([0028] – “after the formation of the spacer 42, another dry etching process is performed. Using the spacer 42, the trench top oxide layer 18 and the silicon oxide layer 34 inside the STI trenches 22 and 20 as etching hard mask, gate trench 60 between the deep trench capacitors 12 is etched”) the selected segment of the gate (60 – Fig. 13 – [0028] – “gate trench 60 between the deep trench capacitors 12 is etched” – shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the removing process as taught by Lee into Xie, Cai, and Wang.
An ordinary artisan would have been motivated to use the known technique of Lee in the manner set forth above to produce the predictable results [0009] – “to provide a method of fabricating a recess-gate MOS transistor of DRAM devices in order to solve the above-mentioned problems.”
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Cai, Wang, and Kim et al. (US 20240194536 A1 – hereinafter Kim).
Regarding claim 6, Xie as modified by Cai and Wang, teaches claim 1 from which claim 6 depends. Xie, Cai, and Wang do not expressly disclose the other limitations of claim 6.
However, in an analogous art, Kim teaches
wherein the sidewall spacer (560 – [0096] – “the spacer 560 on a side surface
of the isolation pattern 710 may be formed together with the isolation pattern 710”) comprises low-k silicon oxide ([claim 19] – “the spacers comprise a silicon oxide or a low-k dielectric material”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the sidewall spacer structure as taught by Kim into Xie, Cai, and Wang.
An ordinary artisan would have been motivated to use the known technique of Kim in the manner set forth above to produce the predictable results of [0005] – “a semiconductor device and a method for manufacturing the same having advantages of stably forming fine patterns and improved isolation between adjacent source/drain patterns and adjacent source/drain contact structures.”
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Cai, Wang, and Wang et al. (US 20140151760 A1 – hereinafter Wang-760).
Regarding claim 8, Xie as modified by Cai and Wang, teaches claim 1 from which claim 8 depends. Xie and Cai do not expressly disclose the limitations of claim 8.
However, in an analogous art, Wang teaches
wherein the gate (60) is a sacrificial gate ([0036] – “etching results in the
removal of the portions of metal gate stack 60 exposed through opening 70” – this is interpreted as a sacrificial gate as it is removed, hereinafter ‘SACG’) and the method
further comprises:
removing a remaining portion of the sacrificial gate (SACG) to form a gate cavity (70 – [0036] – “etching results in the removal of the portions of metal gate stack 60 exposed through opening 70”); and
forming a metal gate in the gate cavity.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the sacrificial gate structure as taught by Wang into Xie and Cai.
An ordinary artisan would have been motivated to use the known technique of Wang in the manner set forth above to produce the predictable results as stated above in claim 1.
Xie, Cai, and Wang do not expressly disclose the other limitations of claim 8.
However, in an analogous art, Wang-760 teaches
forming a metal gate in the gate cavity ([0008] – “An aspect of the disclosure further includes removing the at least two dummy gates, forming cavities, and forming metal gates in the cavities”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the metal gate structure as taught by Wang-760 into Xie, Cai, and Wang.
An ordinary artisan would have been motivated to use the known technique of Wang-760 in the manner set forth above to produce the predictable results of [0003] – “methodology for filling gaps between gates without forming voids and without gap-fill removal, and the resulting device.”
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Cai, Wang, Wang-760, and Zang et al. (US 20180286965 A1 – hereinafter Zang).
Regarding claim 15, Xie as modified by Cai and Wang, teaches claim 9 from which claim 15 depends. Xie and Cai do not expressly disclose the limitations of claim 15.
However, in an analogous art, Wang teaches
wherein the gate (60) is a sacrificial gate (SACG), and wherein
the method further comprises:
after forming the insulation feature (76) in the opening (74), removing a remaining portion of the sacrificial gate to form a gate cavity; and
forming a metal gate in the gate cavity before performing the process to etch the selected ILD structure.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the sacrificial gate structure as taught by Wang into Xie and Cai.
An ordinary artisan would have been motivated to use the known technique of Wang in the manner set forth above to produce the predictable results as stated above in claim 1.
Xie, Cai, and Wang do not expressly disclose the other limitations of claim 15.
However, in an analogous art, Wang-760 teaches
the gate cavity (119 – Fig. 1 – {[0018] – “gap 119”}, {[0008] – “An aspect of the disclosure further includes removing the at least two dummy gates, forming cavities, and forming metal gates in the cavities”}) before ([0007] – “filling a gap between adjacent spacers of the at least two dummy gates with a flowable PMD”) performing the process to etch ([0020] – “the dopant retards the wet etch rate of the PMD”) the selected ILD structure (PMD – [Abstract] – “pre-metal dielectric (PMD)”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the metal gate structure as taught by Wang-760 into Xie, Cai, and Wang.
An ordinary artisan would have been motivated to use the known technique of Wang-760 in the manner set forth above to produce the predictable results as stated above in claim 8.
Xie, Cai, Wang, and Wang-760 do not expressly disclose the other limitations of claim 15.
However, in an analogous art, Zang teaches
removing a remaining portion of the sacrificial gate (122 – [0026] – “dummy gates 122 may be removed from dummy gate stacks 120 (e.g., from between spacers 124) such that an openings 128 are created”) to form a gate cavity (128 – [0026] – “dummy gates 122 may be removed from dummy gate stacks 120 (e.g., from between spacers 124) such that an openings 128 are created”); and
forming a metal gate (134 – [0026] – “Openings 128 (FIG. 2) may be filled, e.g., by deposition, with a metal 132 such that a replacement metal gate 134 is formed within ILD 126”) in the gate cavity.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the sacrificial and metal gate structure as taught by Zang into Xie, Cai, Wang, and Wang-760.
An ordinary artisan would have been motivated to use the known technique of Zang in the manner set forth above to produce the predictable results of [0004] – “one commonly employed technique for forming gate structures for either planar or 3D devices involves forming a line-type gate electrode structure above the gate dielectric layer that formed above an active region defined in a semiconductor substrate. As may be desired, the gate structures may be “cut” such that an opening may be formed therein. The opening may be filled with an insulator thereby isolating portions of the gate structures. As IC structures continue to decrease in size, methods of forming structure therein are difficult and costly to form. For example, conventional methods for forming the insulator within the gate structures require multiple depositions and planarizing of the insulator which is both timely and costly.”
Claims 16, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Wang and Ha et al. (US 20200051976 A1 – hereinafter Ha).
Regarding independent claim 16, Xie teaches:
A semiconductor device (10 – Fig. 1 – {[0004] – “FinFET IC 10 “},
{[0003] – “a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device”}) comprising:
a fin (58 – Fig. 15 – [0017] – “plurality of fins 58”) located over a substrate (52
– Fig. 15 – [0017] – “semiconductor substrate 52”);
source/drain features located in recesses formed in the fin;
an insulation feature located between the source/drain features and
extending through the fin and into the substrate, wherein the insulation feature has an uppermost surface, and wherein at the uppermost surface the insulation feature contacts a non-oxide dielectric layer.
Xie does not expressly disclose the other limitations of claim 16.
However, in an analogous art, Wang teaches
source/drain (42 – Fig. 11C – [0035] – “source/drain regions 42 between gate
stacks 60”) features located in recesses (22 – Fig. 11B – [0035] – “portions of STI regions 22 are directly underlying opening 69”) formed in the fin (24’ – Fig. 13A – [0038] – “Protruding fins 24′ (FIG. 13A) and the underlying semiconductor strips 24 are then etched”);
an insulation feature (76 – Fig. 17B – [0040] – “formation of dielectric isolation
region 76 may include depositing a dielectric material into openings 70, 72, and 74” – this is an insulation feature) located between the source/drain (42) features and
extending through the fin (24’) and into the substrate (20 – [0012] – “Substrate 20” – Fig. 11C shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the cavity and insulation structure as taught by Wang into Xie.
An ordinary artisan would have been motivated to use the known technique of Wang in the manner set forth above to produce the predictable results as stated above in claim 1.
Xie and Wang do not expressly disclose the other limitations of claim 16.
However, in an analogous art, Ha teaches
wherein the insulation feature (DB – Fig. 3D – [0047] – “insulating layer DB”) has an uppermost surface (Fig. 3D annotated, see below – hereinafter ‘UP’), and wherein at the uppermost surface (UP) the insulation feature (DB) contacts a non-oxide dielectric layer (130 – Fig. 3D – [0039] – “first interlayer insulating layer 130 and the second interlayer insulating layer 135 may include, e.g., at least one of silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, or the like” – this is interpreted as may include a non-oxide such as silicon nitride).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the insulation structure as taught by Ha into Xie and Wang.
An ordinary artisan would have been motivated to use the known technique of Ha in the manner set forth above to produce the predictable results of [0003] – “With an increase in the integration density of semiconductor devices, it is becoming increasingly difficult to realize transistor performance required by users. To overcome these technical difficulties, various field-effect transistor (FET) structures have been proposed. For example, a high-k dielectric-metal gate structure has been proposed to replace a conventional FET using silicon oxide and polycrystalline silicon as a gate insulating layer and a gate electrode material, respectively.”
Regarding claim 18, Xie as modified by Wang and Ha, teaches claim 16 from which claim 18 depends. Xie and Ha do not expressly disclose the limitations of claim 18.
However, in an analogous art, Wang teaches
wherein an oxide layer (38 – Fig. 16C – [0018] – “gate spacers 38 are formed
of a dielectric material such as silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, silicon oxycarbo-nitride, or the like” – this is interpreted as formed of silicon oxide) contacts a lower portion of the insulation feature (76 – Fig. 16C – [0043] – “Isolation regions 76 separate the source/drain regions of FinFETs”), and wherein an upper portion of the insulation feature (76) is located above the oxide layer (38 – Fig. 16C shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the insulation structure as taught by Wang into Xie.
An ordinary artisan would have been motivated to use the known technique of Wang in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 20, Xie as modified by Wang and Ha, teaches claim 16 from which claim 20 depends. Xie and Wang do not expressly disclose the limitations of claim 20.
However, in an analogous art, Ha teaches
wherein a conductive interconnect (M1 – Fig. 3D – [0040] – “interconnection
M1”) is located above a selected source/drain (120 – Fig. 3D – [0040] – “source or drain region 120”) feature, and wherein a non-oxide dielectric layer (130 and 135 – Fig. 3D – [0039] – “first interlayer insulating layer 130 and the second interlayer insulating layer 135 may include, e.g., at least one of silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, or the like” – this is interpreted as may include a non-oxide such as silicon nitride – elements 130 and 135 are interpreted as the same layer) contacts the conductive interconnect (M1) and the insulation feature (DB).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the interconnect structure as taught by Ha into Xie and Wang.
An ordinary artisan would have been motivated to use the known technique of Ha in the manner set forth above to produce the predictable results as stated above in claim 16.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Wang, Ha, and Kim.
Regarding claim 17, Xie as modified by Wang and Ha, teaches claim 16 from which claim 17 depends. Xie, Wang, and Ha do not expressly disclose the other limitations of claim 17.
However, in an analogous art, Kim teaches
wherein a gate (123 – Fig. 9D – [0061] – “main gate sacrificial pattern 123”) is
located over the fin (area or element 121 in Fig. 9D is a fin), and wherein the insulation feature (620 – Fig. 9D – [0059] – “insulating layer 620”) extends through the gate (123).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the gate and insulation structure as taught by Kim into Xie, Wang, and Ha.
An ordinary artisan would have been motivated to use the known technique of Kim in the manner set forth above to produce the predictable results as stated above in claim 6.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Wang, Ha, and Cai.
Regarding claim 19, Xie as modified by Wang and Ha, teaches claim 16 from which claim 19 depends. Xie and Ha do not expressly disclose the limitations of claim 19.
However, in an analogous art, Wang teaches
the insulation feature (76).
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the insulation structure as taught by Wang into Xie and Ha.
An ordinary artisan would have been motivated to use the known technique of Wang in the manner set forth above to produce the predictable results as stated above in claim 1.
Xie, Wang, and Ha do not expressly disclose the other limitations of claim 19.
However, in an analogous art, Cai teaches
wherein no portion of the insulation feature contacts an oxide layer ([0036] –
“when the sidewall spacers 24 include either a silicon nitride or a silicon oxide, and the first region 20 includes a-C, a dry, O.sub.2-based ashing process may be used to selectively remove the first region 20” – Fig. 5 shows all of the sidewall spacer in the opening removed – this is interpreted that it is free of silicon oxide).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the sidewall spacer structure as taught by Cai into Xie, Wang, and Ha.
An ordinary artisan would have been motivated to use the known technique of Cai in the manner set forth above to produce the predictable results as stated above in claim 1.
Pertinent Art
For the benefits of the Applicant, US 20240170552 A1 is cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including the cavity structure.
Conclusion
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/GRA/
Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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