DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-9, 11-14, 16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Qian et al. (US 20160085899 A1) herein after “Qian” in view of Yang et al. (US 20230387030 A1) herein after “Yang”.
Regarding claim 1, Fig. 5 of Qian discloses a semiconductor structure (Fig. 5, routing configuration 500, ¶ [0045]) comprising:
a first routing layer (Fig. 5, routing layer 210, ¶ [0027]) including a plurality of first signal wires (Fig. 5, signal traces 209, ¶ [0029]) and a plurality of first ground wires (Fig. 5, ground traces 206, ¶ [0029]) that are arranged alternately in a first horizontal direction;
a second routing layer (Fig. 5, routing layer 212, ¶ [0027]) including a plurality of second signal wires (209) and a plurality of second ground wires (206) that are alternately arranged in the first horizontal direction and disposed on the first routing layer (210);
a third routing layer (Fig. 5, routing layer 214, ¶ [0027]) including a plurality of third signal wires (209) and a plurality of third ground wires (206) that are alternately arranged in the first horizontal direction and disposed on the second routing layer (212); and
a plurality of vias (Fig. 5, vias 213, ¶ [0036]) connecting the plurality of first ground wires (206), the plurality of second ground wires (206), and the plurality of third ground wires (206) to each other,
wherein the plurality of first signal wires (209), the plurality of second signal wires (209), the plurality of third signal wires (209), the plurality of first ground wires (206), the plurality of second ground wires (206), and the plurality of third ground wires (206) extend in a second horizontal direction intersecting the first horizontal direction,
wherein the plurality of first signal wires (209), the plurality of second signal wires (209), and the plurality of third signal wires (209) overlap each other, and
wherein the plurality of first ground wires (206), the plurality of second ground wires (206), and the plurality of third ground wires (206) overlap each other.
Qian fails to disclose wherein each signal wire among the plurality of first signal wires, the plurality of second signal wires, and the plurality of third signal wires is separated from remaining signal wires.
In the similar field of endeavor of wiring substrates, Fig. 4 of Yang discloses wherein each signal wire among the plurality of first signal wires (Fig. 4, first signal traces 101, ¶ [0018]), the plurality of second signal wires (Fig. 4, second signal traces 201, ¶ [0023]), and the plurality of third signal wires (Fig. 4, third signal traces 301, ¶ [0029]) is separated from remaining signal wires (“the first signal, the second signal, the third signal and the fourth signal can be… all different”, ¶ [0054]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Qian with the separate signal wires as disclosed by Yang, to improve impedance distribution and signal quality (see Yang, ¶ [0054]).
Regarding claim 2, Qian and Yang together disclose the semiconductor structure of claim 1 as applied above, but Qian fails to disclose wherein
each signal wire among the plurality of first signal wires, the plurality of second signal wires, and the plurality of third signal wires is configured to route a signal different from signals routed by the remaining signal wires.
In the similar field of endeavor of wiring substrates, Fig. 4 of Yang discloses wherein
each signal wire among the plurality of first signal wires (101), the plurality of second signal wires (201), and the plurality of third signal wires (301) is configured to route a signal different from signals routed by the remaining signal wires (“the first signal, the second signal, the third signal and the fourth signal can be… all different”, ¶ [0054]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Qian with the separate signal wires as disclosed by Yang, to improve impedance distribution and signal quality (see Yang, ¶ [0054]).
Regarding claim 4, Qian and Yang together disclose the semiconductor structure of claim 1 as applied above, but Qian fails to disclose wherein
a pitch between each signal wire among the plurality of first signal wires, the plurality of second signal wires, and the plurality of third signal wires and a ground wire adjacent to each signal wire in the first horizontal direction is smaller than a pitch between each signal wire among the plurality of first signal wires, the plurality of second signal wires, and the plurality of third signal wires and a different signal wire adjacent to each signal wire in a vertical direction.
In the similar field of endeavor of wiring substrates, Fig. 4 of Yang discloses wherein
a pitch between each signal wire among the plurality of first signal wires (101), the plurality of second signal wires (201), and the plurality of third signal wires (301) and a ground wire adjacent to each signal wire in the first horizontal direction is smaller than a pitch between each signal wire among the plurality of first signal wires (101), the plurality of second signal wires (201), and the plurality of third signal wires (301) and a different signal wire adjacent to each signal wire in a vertical direction.
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Qian with the pitch as disclosed by Yang, to obtain higher data transfer rate and better eye width (see Yang, ¶ [0055-0056]).
Regarding claim 5, Qian and Yang together disclose the semiconductor structure of claim 1 as applied above, and Qian further discloses wherein
each signal wire among the plurality of first signal wires (209), the plurality of second signal wires (209), and the plurality of third signal wires (209), and each ground wire among the plurality of first ground wires (206), the plurality of second ground wires (206), and the plurality of third ground wires (206) include an elongated shape.
Regarding claim 6, Qian and Yang together disclose the semiconductor structure of claim 1 as applied above, and Fig. 5 of Qian further discloses comprising
a fourth routing layer (Fig. 5, routing layer 216, ¶ [0027]) including a plurality of fourth signal wires (209) and a plurality of fourth ground wires (206) that are alternately arranged in the first horizontal direction and disposed on the third routing layer (214),
wherein the plurality of vias (213) also connect the plurality of third ground wires (206) and the plurality of fourth ground wires (206) to each other,
wherein the plurality of fourth signal wires (209) and the plurality of fourth ground wires (206) extend in a second horizontal direction intersecting the first horizontal direction,
wherein the plurality of first signal wires (209), the plurality of second signal wires (209), the plurality of third signal wires (209), and the plurality of fourth signal wires (209) overlap each other, and
wherein the plurality of first ground wires (206), the plurality of second ground wires (206), the plurality of third ground wires (206), and the plurality of fourth ground wires (206) overlap each other.
Qian fails to disclose wherein each signal wire among the plurality of first signal wires, the plurality of second signal wires, the plurality of third signal wires, and the plurality of fourth signal wires is separated from remaining signal wires.
In the similar field of endeavor of wiring substrates, Fig. 4 of Yang discloses wherein each signal wire among the plurality of first signal wires (101), the plurality of second signal wires (201), the plurality of third signal wires (301), and the plurality of fourth signal wires (401) is separated from remaining signal wires (“the first signal, the second signal, the third signal and the fourth signal can be… all different”, ¶ [0054]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Qian with the separate signal wires as disclosed by Yang, to improve impedance distribution and signal quality (see Yang, ¶ [0054]).
Regarding claim 7, Qian and Yang together disclose the semiconductor structure of claim 1 as applied above, and Fig. 5 of Qian further discloses comprising
a fourth routing layer (216), or a fourth routing layer (216) to an (N+4)th routing layer, where N is a natural number of 1 or more,
wherein the fourth routing layer (216), or each of the fourth to (N+4)th routing layers, includes a plurality of signal wires and a plurality of ground wires that are arranged alternately in the first horizontal direction.
Regarding claim 8, Fig. 5 of Qian discloses a semiconductor structure (500) comprising:
a first routing layer (210) including a plurality of first signal wires (209) and a plurality of first ground wires (206) that are arranged alternately in a first horizontal direction;
a first connection layer including a plurality of first vias (213) connected to the plurality of first ground wires (206) and disposed on the first routing layer (210);
a second routing layer (212) including a plurality of second signal wires (209) and a plurality of second ground wires (206) that are alternately arranged in the first horizontal direction and disposed on the first connection layer, wherein the plurality of second ground wires (206) are connected to the plurality of first vias (213);
a second connection layer including a plurality of second vias (213) connected to the plurality of second ground wires (206) and disposed on the second routing layer (212);
a third routing layer (214) including a plurality of third signal wires (209) and a plurality of third ground wires (206) that are alternately arranged in the first horizontal direction and disposed on the second connection layer, wherein the plurality of third ground wires (206) are connected to the plurality of second vias (213); and
a dielectric (Fig. 5, electrically insulative material 204, ¶ [0028]) surrounding the plurality of first signal wires (209), the plurality of second signal wires (209), and the plurality of third signal wires (209), the plurality of first ground wires (206), the plurality of second ground wires (206), and the plurality of third ground wires (206), and the plurality of first vias (213) and the plurality of second vias (213),
wherein the plurality of first signal wires (209), the plurality of second signal wires (209), the plurality of third signal wires (209), the plurality of first ground wires (206), the plurality of second ground wires (206), and the plurality of third ground wires (206) extend in a second horizontal direction intersecting the first horizontal direction,
wherein the plurality of first signal wires (209), the plurality of second signal wires (209), and the plurality of third signal wires (209) overlap each other, and
wherein the plurality of first ground wires (206), the plurality of second ground wires (206), and the plurality of third ground wires (206) overlap each other.
Qian fails to disclose wherein each signal wire among the plurality of first signal wires, the plurality of second signal wires, and the plurality of third signal wires is separated from remaining signal wires.
In the similar field of endeavor of wiring substrates, Fig. 4 of Yang discloses wherein each signal wire among the plurality of first signal wires (101), the plurality of second signal wires (201), and the plurality of third signal wires (301) is separated from remaining signal wires (“the first signal, the second signal, the third signal and the fourth signal can be… all different”, ¶ [0054]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Qian with the separate signal wires as disclosed by Yang, to improve impedance distribution and signal quality (see Yang, ¶ [0054]).
Regarding claim 9, Qian and Yang together disclose the semiconductor structure of claim 8 as applied above, and Qian further discloses wherein
the semiconductor structure includes a silicon interposer (“the bridge 105 may be composed of silicon”, “The routing configuration 104 may be implemented in other suitable interconnect applications in other embodiments including, for example…, interposer”, ¶ [0022] and [0035]).
Regarding claim 11, Qian and Yang together disclose the semiconductor structure of claim 8 as applied above, but the combination fails to explicitly disclose wherein
a pitch between each signal wire among the plurality of first signal wires, the plurality of second signal wires, and the plurality of third signal wires and a different signal wire adjacent to each signal wire in a vertical direction is in a range of 2 μm to 10 μm.
However, Yang does disclose that the spacing between adjacent traces and dielectric thicknesses can be used to optimize signal integrity and data transfer rate (see Yang, ¶ [0056]). Therefore, it would have been obvious to one of ordinary skill in the art to arrive at the claimed vertical pitch through optimization of the trace spacing and dielectric thickness to obtain the optimal signal integrity and data transfer rate and/or because it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05, citing In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Regarding claim 12, Figs. 1 and 4 of Qian disclose a semiconductor package (Fig. 1, package assembly 100, ¶ [0019]) comprising:
a substrate (Fig. 1, circuit board 106, ¶ [0019]);
an interconnection structure (Fig. 1, package substrate 104, ¶ [0019]) on the substrate (106);
a semiconductor die (Fig. 1, dies 102a, 102b, ¶ [0019]) on the interconnection structure (104);
wherein the interconnection structure (104) includes:
a first routing layer (210) including a plurality of first signal wires (209) and a plurality of first ground wires (206) that are arranged alternately in a first horizontal direction;
a second routing layer (212) including a plurality of second signal wires (209) and a plurality of second ground wires (206) that are alternately arranged in the first horizontal direction and disposed on the first routing layer (210);
a third routing layer (214) including a plurality of third signal wires (209) and a plurality of third ground wires (206) that are alternately arranged in the first horizontal direction and disposed on the second routing layer (212); and
a plurality of vias (213) connecting the plurality of first ground wires (206), the plurality of second ground wires (206), and the plurality of third ground wires (206) to each other,
wherein the plurality of first signal wires (209), the plurality of second signal wires (209), and the plurality of third signal wires (209), the plurality of first ground wires (206), the plurality of second ground wires (206), and the plurality of third ground wires (206) extend in a second horizontal direction intersecting the first horizontal direction,
wherein the plurality of first signal wires (209), the plurality of second signal wires (209), and the plurality of third signal wires (209) overlap each other, and
wherein the plurality of first ground wires (206), the plurality of second ground wires (206), and the plurality of third ground wires (206) overlap each other.
Qian fails to disclose a semiconductor stacking structure on the interconnection structure,
wherein each signal wire among the plurality of first signal wires, the plurality of second signal wires, and the plurality of third signal wires is separated from remaining signal wires.
In the similar field of endeavor of wiring substrates, Figs. 4-5 of Yang discloses a semiconductor stacking structure (Fig. 5, memory chip 501, ¶ [0048]) on the interconnection structure (Fig. 5, interposer 505, ¶ [0048]),
wherein each signal wire among the plurality of first signal wires (101), the plurality of second signal wires (201), and the plurality of third signal wires (301) is separated from remaining signal wires (“the first signal, the second signal, the third signal and the fourth signal can be… all different”, ¶ [0054]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Qian with the separate signal wires and stacking structure as disclosed by Yang, to improve impedance distribution and signal quality and increase functionality (see Yang, ¶ [0054] and [0056]).
Regarding claim 13, Qian and Yang together disclose the semiconductor package of claim 12 as applied above, and Fig. 1 of Qian further discloses wherein
an upper surface of the substrate (106) contacts a lower surface of the interconnection structure (104) (Fig. 1, “The package substrate 104 may be coupled with a circuit board 106 using second-level interconnect (SLI) structures such as, for example, solder balls 108 or other suitable package-level interconnect structures”, ¶ [0019]).
Regarding claim 14, Qian and Yang together disclose the semiconductor package of claim 12 as applied above, and Qian further discloses wherein
each signal wire among the plurality of first signal wires (209), the plurality of second signal wires (209), and the plurality of third signal wires (209) is electrically connected to at least one of the semiconductor die (102) or the semiconductor stacking structure (“signal traces 209 configured to route I/O signals of the dies”, ¶ [0029]).
Regarding claim 16, Qian and Yang together disclose the semiconductor package of claim 12 as applied above, and Qian further discloses wherein
the plurality of first ground wires (206), the plurality of second ground wires (206), and the plurality of third ground wires (206) are electrically connected to the semiconductor die (102) or the semiconductor stacking structure (“ground traces 206 configured to route a ground connection… of the dies”, ¶ [0029]).
Regarding claim 18, Qian and Yang together disclose the semiconductor package of claim 12 as applied above, and Qian further discloses wherein
the semiconductor die (102) includes a system on a chip (SoC) (“the die 102a or 102b may include, or be a part of a processor, memory, system-on-chip (SoC)”, ¶ [0022]).
Regarding claim 19, Qian and Yang together disclose the semiconductor package of claim 12 as applied above, but Qian fails to disclose wherein
the semiconductor stacking structure includes a high bandwidth memory (HBM).
In the similar field of endeavor of wiring substrates, Fig. 5 of Yang discloses wherein
the semiconductor stacking structure (501) includes a high bandwidth memory (HBM) (“the memory chip 501 can be implemented by high-bandwidth memory”, ¶ [0053]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Qian with the stacking structure as disclosed by Yang, to increase functionality (see Yang, ¶ [0056]).
Regarding claim 20, Qian and Yang together disclose the semiconductor package of claim 12 as applied above, and Qian further discloses wherein
the substrate (106) includes a printed circuit board (PCB) (“The circuit board 106 may be a printed circuit board (PCB)”, ¶ [0025]).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Qian (US 20160085899 A1) and Yang (US 20230387030 A1) in further view of Wang et al. (US 20180366416 A1) herein after “Wang”.
Regarding claim 3, Qian and Yang together disclose the semiconductor structure of claim 1 as applied above, and Qian discloses the plurality of first signal wires, the plurality of second signal wires, and the plurality of third signal wires, but the combination fails to disclose wherein
a pitch between each signal wire and a ground wire adjacent to each signal wire in the first horizontal direction is smaller than a height of each signal wire.
In the similar field of endeavor of semiconductor wiring substrates, Fig. 3 of Wang discloses a pitch between each signal (Fig. 3, signal line “S”, ¶ [0026]) and a ground wire (Fig. 3, grounding line “G”, ¶ [0026]) in the first horizontal direction is smaller than the height of each signal wire (S).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Qian with the pitch as disclosed by Wang, to enhance signal shielding performance (see Wang, ¶ [0036]).
Claims 10, 15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Qian (US 20160085899 A1) and Yang (US 20230387030 A1) in further view of Agarwal et al. (US 20220051989 A1) herein after “Agarwal”.
Regarding claim 10, Qian and Yang together disclose the semiconductor structure of claim 8 as applied above, but the combination fails to explicitly disclose wherein
the semiconductor structure includes a redistribution layer structure.
In the similar field of endeavor of semiconductor modules, Fig. 7 of Agarwal discloses the semiconductor structure (Fig. 7, semiconductor device 700, ¶ [0074]) includes a redistribution layer structure (Fig. 7, redistribution layer 761, ¶ [0075]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Qian with the redistribution layer as disclosed by Agarwal, to provide electrical connections to multiple components (see Agarwal, ¶ [0042]).
Regarding claim 15, Qian and Yang together disclose the semiconductor structure of claim 12 as applied above, and Qian further disclose the plurality of first signal wires (209), the plurality of second signal wires (209), and the plurality of third signal wires (209), but Qian and Yang fail to explicitly disclose each signal wire is electrically connected to the substrate.
In the similar field of endeavor of semiconductor modules, Fig. 7 of Agarwal discloses each signal wire is electrically connected to the substrate (“the conductive bumps (765) and conductive pillars (763) provide a conductive pathway from the surface of the substrate (708) to the redistribution layer (761) connecting the semiconductor module (702), peripheral module (704), and interconnecting die (764) for providing the conveyance of input/output signals”, ¶ [0078]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Qian with the connections as disclosed by Agarwal, to control components (see Agarwal, ¶ [0078]).
Regarding claim 17, Qian and Yang together disclose the semiconductor structure of claim 12 as applied above, and Qian further disclose the plurality of first ground wires (206), the plurality of second ground wires (206), and the plurality of third ground wires (206), but Qian and Yang fail to explicitly disclose the ground wires are electrically connected to the substrate.
In the similar field of endeavor of semiconductor modules, Fig. 7 of Agarwal discloses the ground wires are electrically connected to the substrate (“the conductive bumps (765) and conductive pillars (763) provide a conductive pathway from the surface of the substrate (708) to the redistribution layer (761) connecting the semiconductor module (702), peripheral module (704), and interconnecting die (764) for providing the conveyance of… ground to those components”, ¶ [0078]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Qian with the connections as disclosed by Agarwal, to control components (see Agarwal, ¶ [0078]).
Conclusion
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/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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