Prosecution Insights
Last updated: October 04, 2026
Application No. 18/759,464

CHARGE BASED SWITCHED MATRIX AND METHOD THEREFOR

Non-Final OA §112
Filed
Jun 28, 2024
Priority
Oct 09, 2019 — divisional of 12/061,975
Examiner
MILLER, ALAN S
Art Unit
Tech Center
Assignee
Aistorm Inc.
OA Round
1 (Non-Final)
71%
Grant Probability
Favorable
1-2
OA Rounds
10m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 71% — above average
71%
Career Allowance Rate
631 granted / 894 resolved
+10.6% vs TC avg
Strong +27% interview lift
Without
With
+26.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
15 currently pending
Career history
912
Total Applications
across all art units

Statute-Specific Performance

§101
36.3%
-3.7% vs TC avg
§103
32.2%
-7.8% vs TC avg
§102
6.6%
-33.4% vs TC avg
§112
18.4%
-21.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 894 resolved cases

Office Action

§112
DETAILED ACTION This action is in response to the application filed 28 June 2024, claiming benefit back to 9 October 2019. Claims 8 and 10 – 16 are pending and have been examined. This action is Non-Final. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Divisional This application is a divisional application of U.S. application no. 16/597,522, filed on 9 October 2019, now U.S. Patent 12,061,975 (“Parent Application”). See MPEP §201.06. In accordance with MPEP §609.02 A. 2 and MPEP §2001.06(b) (last paragraph), the Examiner has reviewed and considered the prior art cited in the Parent Application. Also in accordance with MPEP §2001.06(b) (last paragraph), all documents cited or considered ‘of record’ in the Parent Application are now considered cited or ‘of record’ in this application. Additionally, Applicant(s) are reminded that a listing of the information cited or ‘of record’ in the Parent Application need not be resubmitted in this application unless Applicants desire the information to be printed on a patent issuing from this application. See MPEP §609.02 A. 2. Finally, Applicants are reminded that the prosecution history of the Parent Application is relevant in this application. See e.g., Microsoft Corp. v. Multi-Tech Sys., Inc., 357 F.3d 1340, 1350, 69 USPQ2d 1815, 1823 (Fed. Cir. 2004) (holding that statements made in prosecution of one patent are relevant to the scope of all sibling patents). Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claim 8 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention. It has been held that to satisfy the written description requirement, a patent specification must describe the claimed invention in sufficient detail that one skilled in the art can reasonably conclude that the inventor had possession of the claimed invention. (See, e.g., Moba, B.V. v. Diamond Automation, Inc., 325 F.3d 1306, 1319, 66 USPQ2d 1429, 1438 (Fed. Cir. 2003); Vas-Cath, Inc. v. Mahurkar, 935 F.2d at 1563, 19 USPQ2d at 1116). Further, it has been held that a showing of possession alone does not cure the lack of a written description. An applicant shows possession of the claimed invention by describing the claimed invention with all of its limitations using such descriptive means as words, structures, figures, diagrams, and formulas that fully set forth the claimed invention. (Lockwood v. Amer. Airlines, Inc., 107 F.3d 1565, 1572, 41 USPQ2d 1961, 1966 (Fed. Cir. 1997)). Claim 8 recites the limitation a a device to increase an effective number of neurons, or to produce virtual neurons, in a network, wherein the device separates neuron operations into time frames, wherein at each frame connections are modified such that a new connection reuses a neuron as if it were an independent neuron; however, except in the background of the invention (which merely restated the claim), none of these features or limitations appear to be disclosed in Applicant’s disclosure in such a way to satisfy the written description requirement. For example, the disclosure does not appear to teach or disclose separate neuron operations into time frames, no recitation of time frames, no description or disclosure regarding a modification of connections such that a new connection reuses a neuron as if it were an independent neuron; no device performing this, no increase of effective number of neurons, nor is can Examiner find any disclosure of a device that has this intended use of increasing an effective number of neurons, or to producing virtual neurons. As shown below, these paragraphs provide the closest disclosure to the claimed invention; however they do not appear, either alone or in combination with any other paragraph, the claimed limitations. For example, paragraph [0006], which is in the background of the disclosure, is the only paragraph that actually discusses the claim limitations: [0006] A neural network which can communicate information at very high data rates, and further which allows fast dynamic reconnection of the switch matrix or communications network may also be used to virtually increase the effective number of neurons by re-connecting neurons very quickly and re-using them based upon a time framed approach. This may increase the number of effective neurons by the number of frames that is used. It may alternatively or may also allow recurrent network functionality. For example, if there were sixteen time frames or time slots, then in the first frame one might have one network connectivity, in the second time frame another network connectivity and so forth. The result would look to the user like a network which is sixteen times the size. The only other paragraphs that disclose time frames or time slots, virtual neurons, or reusing neurons (i.e., zcells) appear below: [0084] The second frame information is stored in the charge reservoirs or short term memory after the initial frame and only once the last controller 84 indicates that it is finished with its first frame activities will the controllers 84 begin the second frame. The controllers 84 will also handle execution control such that neuron connections which represent virtual neurons (re-used neurons) will be connected in sequence. In this way a smaller number of neurons may simulate a much bigger neural network due to the speed that can be achieve using the switch charge (pulse networking coupled neurons) concept. [0089] FIG. 6 illustrates the many different connectivity types that are possible in a neural network. It is desirable to be able to make these connections so as to reuse zcells to produce virtual neurons, or for recurrent neural networks in a dynamic way. FIG. 7 illustrates how a succession of crossbars might be used to connect many neurons together at the same time over distance. The common thread are simultaneous pulses driven to a number of different neurons. By utilizing time frames, different neurons could be dynamically connected at different times and pulses might travel in different directions to implement the functionality illustrated in FIG. 6. As such, Applicant’s disclosure fails to provide a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Allowable Subject Matter Claim 8 would be allowable if the rejection of 35 USC 112(a) rejection is overcome. Claims 10 – 16 are allowed. See e.g., Parent Application, 16/597,522, filed on 9 October 2019, now U.S. Patent 12,061,975. Further, the closest prior art includes Engeler (U.S. 5,039,870), disclosing and directed to weighted summation circuits having different-weight ranks of capacitive structures; Yoshizawa et al. (U.S. 5,131,072), disclosing and directed to a neurocomputer with analog signal bus; Adler (U.S. 5,261,035), disclosing and directed to neural network architecture based on summation of phase-coherent alternating current signals; Nestler et al. (U.S. 2019/0080231), disclosing and directed to analog switched-capacitor neural network; Tran et al. (U.S. 2019/0341110), disclosing and directed to method and apparatus for high voltage generation for analog neural memory in deep learning artificial neural network; and Far (U.S. 10,700,695), disclosing and directed to mixed-mode quarter square multipliers for machine learning. Conclusion The prior art made of record and not relied upon considered pertinent to Applicant’s disclosure. Matsugu, Masakazu US 20030004907 A1 Pulse signal circuit, parallel processing circuit, pattern recognition system, and image input system Schie; David US 20140344200 A1 Low Power Integrated Analog Mathematical Engine MacFarlane; Douglas James Wallace US 20100277152 A1 Charge Pump Circuit And Methods Of Operation Thereof Ramadass; Yogesh K. et al. US 20090072800 A1 Circuit and Method for a Fully Integrated Switched-Capacitor Step-Down Power Converter Zojer; Bernhard et al. US 20170047841 A1 System and Method for a Switch Having a Normally-on Transistor and a Normally-off Transistor Krymski; Alexander I. US 6147519 A Low-voltage comparator with wide input voltage swing Kuo; James R. US 5483184 A Programmable CMOS bus and transmission line receiver Sen; Subhajit et al. US 7053684 B1 Reduced jitter charge pumps and circuits and systems utilizing the same Arima; Yutaka et al. US 5148514 A Neural network integrated circuit device having self-organizing function Zhang; Haoran et al. US 6445623 B1 Charge pumps with current sources for regulation Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALAN S MILLER whose telephone number is (571)270-5288. The examiner can normally be reached on M-F 10am-6pm. Examiner’s fax phone number is (571) 270-6288. Examiner interviews are available via telephone and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Beth Boswell can be reached at (571) 272-6737. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALAN S MILLER/Primary Examiner, Art Unit 3625
Read full office action

Prosecution Timeline

Jun 28, 2024
Application Filed
Aug 31, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12737707
Method for a Plant Operation Optimization Component
2y 3m to grant Granted Sep 15, 2026
Patent 12711450
SYSTEM AND METHOD TO EVALUATE ENTERPRISE DATA ANALYST TRAINING CANDIDATES
3y 5m to grant Granted Aug 18, 2026
Patent 12705636
METHODS AND APPARATUS TO DETERMINE RATINGS INFORMATION FOR ONLINE MEDIA PRESENTATIONS
1y 11m to grant Granted Aug 11, 2026
Patent 12705559
METHOD FOR DETERMINING A PROJECT FLOW, ELECTRONIC DEVICE, AND STORAGE MEDIUM
1y 11m to grant Granted Aug 11, 2026
Patent 12694354
SYSTEMS AND METHODS FOR CONVERTING DIAGRAMS TO WORKFLOWS
2y 2m to grant Granted Jul 28, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
71%
Grant Probability
97%
With Interview (+26.6%)
3y 1m (~10m remaining)
Median Time to Grant
Low
PTA Risk
Based on 894 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month