DETAILED ACTION
This action is responsive to the claims filed 30 Mar 2026 and the Information Disclosure Statement filed 17 Sep 2024. Claims 2-10 and 19-21 are pending, claims 11-18 have been cancelled. Claims 1 and 19 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
In the letter dated 30 Mar 2026, the applicant elected claims 2-10 and 19-21 for examination. Claims 11-18 have been cancelled.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 17 Sep 2024 is acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Allowable Subject Matter
Claims 5, 6, 8, and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 2 – 4, 7, 10, and 19 – 21 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim, W., U.S. Patent Application Publication 2023/0206981 with Foreign Priority Date 27 Dec 2021 (“Kim”).
Regarding claim 2, Kim teaches:
A memory system, comprising: one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: (Kim, fig 1, “[0038] Referring to FIG. 1, the memory device may include a memory cell array 10, a row control circuit 11, a sense amplifier SENSE AMP 17, a column control circuit COLUMN CONTROL CIRCUIT 18, a command decoder COMMAND DECODER 12.”; a memory systems with circuitry to control the memory cells).
receive, during a duration in which one or more voltage rails configured to provide power to the memory system are deactivated, power at a first voltage rail of the one or more voltage rails, (Kim, fig 1, “[0064] In accordance with an embodiment, among the plurality of word lines WL<l:16>, the GROUP MANAGEMENT CIRCUIT 14 classifies four refresh addresses RADD indicating the first to fourth word lines WL<l:4> as a first refresh address group, classifies four refresh addresses RADD indicating the fifth to eighth word lines WL<5:8> as a second refresh address group, [0063] Then, the SUPPLY CONTROL CIRCUIT 15 may activate two signals corresponding to the current refresh address group and the subsequent refresh address group among the N group control signals WC<l:4> and deactivate the remaining signals in the section in which the self-refresh operation is performed.”; a memory system Group Management Circuit 14 that can deactivate a portion of the memory array, in this case WL5-WL16 for a duration of time).
wherein a second voltage rail of the one or more voltage rails remains deactivated during receiving power at the first voltage rail; and (Kim, fig 1, “[0063] Furthermore, the supply of power to the remaining word line control circuits except for the current refresh address group and the subsequent refresh address group among the plurality of word line control circuits WL CC<l:16> may be disabled in response to the remaining deactivated group control signals.”; that “remaining word lines” WL5-WL16 may be disabled or deactivated for refresh operations duration).
perform a self-refresh operation of the memory system based at least in part on receiving power at the first voltage rail. (Kim, fig 1, “[0063] Consequently, the supply of power to a set number of word line control circuits corresponding to each of the current refresh address group and the subsequent refresh address group among the plurality of word line control circuits WL CC<l:16> may be enabled in response to the two activated group control signals.”; that “a set number of word lines” WL1-WL4 are enabled for the self-refresh operations).
Regarding claim 3, Kim teaches:
The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: operate the memory system in a first power mode associated with the one or more voltage rails being deactivated, (Kim, fig 1, “[0063] Consequently, the supply of power to a set number of word line control circuits corresponding to each of the current refresh address group and the subsequent refresh address group among the plurality of word line control circuits WL CC<l:16> may be enabled in response to the two activated group control signals.”; that “a set number of word lines” WL1-WL4 are enabled for the self-refresh operations in a “first power mode” which self-refreshes a portion of the memory cells).
wherein receive power at the first voltage rail is based at least in part on operating the memory system in the first power mode. (Kim, fig 1, “[0063] Furthermore, the supply of power to the remaining word line control circuits except for the current refresh address group and the subsequent refresh address group among the plurality of word line control circuits WL CC<l:16> may be disabled in response to the remaining deactivated group control signals.”; that “remaining word lines” WL5-WL16 may be disabled or deactivated for refresh operations duration in a “first power mode”).
Regarding claim 4, Kim teaches:
The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: determine whether a second duration satisfies a threshold based at least in part on receiving power at the first voltage rail, (Kim, fig 1, “[0108] At this time, the GROUP MANAGEMENT CIRCUIT 14 may generate the N current group signals WGCl<l:4> corresponding to the N refresh address groups, respectively, and generate the N subsequent group signals WGC2<1:4> by signal-shifting the N current group signals WGCl <1:4>.”; a timing scheme with at least a first duration of self-refresh for a first bank of word lines is activated. Note: as described in applicant’s specification, “a second duration satisfies a threshold” can be interpreted as counting a number of clock cycles for a self-refresh operation).
wherein perform the self-refresh operation of the memory system is based at least in part on determining that the second duration satisfies the threshold. (Kim, fig 8, “[0152] Before a first refresh address RADD is generated after the entry into the self-refresh section SELF-REFRESH, the first group control signal WC<l> of the four group control signals WC<l:4> may be activated and the remaining group control signals WC<2:4> may be deactivated (1000). [0153] Furthermore, since the four subsequent group signals WGC2<1:4> may be generated by signal-shifting the four current group signals WGCl<l:4>, the first subsequent group signal WGC2<1> of the four subsequent group signals WGC2<1:4> may be activated and the remaining subsequent group signals WGC2<2:4> may be deactivated (1000).”; a timing scheme with at least a second duration of self-refresh for a second bank of word lines is activated while other word lines are deactivated).
Regarding claim 7, Kim teaches:
The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: determine whether a temperature of the memory system satisfies a threshold based at least in part on receiving power at the first voltage rail, (Kim, fig 1, “[0099] The REFRESH CONTROL CIRCUIT 13 in accordance with an embodiment of the present disclosure may include… a temperature measuring circuit TEMPERATURE MEASURING CIRCUIT 33.”; a self-refresh cycle that can be based on temperature and voltage controls from claim 1 can be applied based on the refresh control circuit 13).
wherein perform the self-refresh operation is based at least in part on determining that the temperature of the memory system satisfies the threshold. (Kim, fig 1, “[0101] The SELF REFRESH COMMAND GENERATING CIRCUIT 31 may generate the self-refresh command SCMD every set cycle …The set cycle may be varied in response to a temperature information signal TEMP applied by the TEMPERATURE MEASURING CIRCUIT 33”; that the “set cycle” can be based on temperature measuring circuits in the memory).
Regarding claim 10, Kim teaches:
The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: determine whether the self-refresh operation is complete; (Kim, fig 1, “[0100] The SELF REFRESH ENABLE SIGNAL GENERATING CIRCUIT 30 may generate the self-refresh enable signal SREN in response to the entry command SRE for entering the self-refresh operation and the exit command SRX for exiting from the self-refresh operation,”; that a self-refresh cycle, as described in claim 1 can produce the necessary signals to refresh a memory array).
activate a timer based at least in part on determining that the self-refresh operation is complete; and perform a second self-refresh operation based at least in part on determining that a second duration associated with the timer satisfies a threshold. (Kim, fig 1, “[0101] The SELF REFRESH COMMAND GENERATING CIRCUIT 31 may generate the self-refresh command SCMD every set cycle in the self-refresh section in which the self-refresh enable signal SREN is activated.”; that after as “set cycle”, the system may generate a second self-refresh cycle).
Regarding claim 19, Kim teaches:
A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to: receive, (Kim, fig 1, “[0038] Referring to FIG. 1, the memory device may include a memory cell array 10, a row control circuit 11, a sense amplifier SENSE AMP 17, a column control circuit COLUMN CONTROL CIRCUIT 18, a command decoder COMMAND DECODER 12. [0032] In this disclosure, various units, circuits, or other components may be described or claimed as “configured to” perform a task or tasks…. the “configured to” language includes hardware-for example, circuits, memory storing program instructions executable to implement the operation, etc.”; a memory systems with circuitry to control the memory cells; that hardware memory can store program instructions (hardware memory comprises non-transitory medium)).
during a duration in which one or more voltage rails configured to provide power to a memory system are deactivated, power at a first voltage rail of the one or more voltage rails, (Kim, fig 1, “[0064] In accordance with an embodiment, among the plurality of word lines WL<l:16>, the GROUP MANAGEMENT CIRCUIT 14 classifies four refresh addresses RADD indicating the first to fourth word lines WL<l:4> as a first refresh address group, classifies four refresh addresses RADD indicating the fifth to eighth word lines WL<5:8> as a second refresh address group, [0063] Then, the SUPPLY CONTROL CIRCUIT 15 may activate two signals corresponding to the current refresh address group and the subsequent refresh address group among the N group control signals WC<l:4> and deactivate the remaining signals in the section in which the self-refresh operation is performed.”; a memory system Group Management Circuit 14 that can deactivate a portion of the memory array, in this case WL5-WL16 for a duration of time).
wherein a second voltage rail of the one or more voltage rails remains deactivated during receiving power at the first voltage rail; and (Kim, fig 1, “[0063] Furthermore, the supply of power to the remaining word line control circuits except for the current refresh address group and the subsequent refresh address group among the plurality of word line control circuits WL CC<l:16> may be disabled in response to the remaining deactivated group control signals.”; that “remaining word lines” WL5-WL16 may be disabled or deactivated for refresh operations duration).
perform a self-refresh operation of the memory system based at least in part on receiving power at the first voltage rail. (Kim, fig 1, “[0063] Consequently, the supply of power to a set number of word line control circuits corresponding to each of the current refresh address group and the subsequent refresh address group among the plurality of word line control circuits WL CC<l:16> may be enabled in response to the two activated group control signals.”; that “a set number of word lines” WL1-WL4 are enabled for the self-refresh operations).
Regarding claim 20, Kim teaches:
The non-transitory computer-readable medium of claim 19, wherein the instructions are further executable by the one or more processors to: operate the memory system in a first power mode associated with the one or more voltage rails being deactivated, (Kim, fig 1, “[0063] Consequently, the supply of power to a set number of word line control circuits corresponding to each of the current refresh address group and the subsequent refresh address group among the plurality of word line control circuits WL CC<l:16> may be enabled in response to the two activated group control signals.”; that “a set number of word lines” WL1-WL4 are enabled for the self-refresh operations in a “first power mode” which self-refreshes a portion of the memory cells).
wherein receive power at the first voltage rail is based at least in part on operating the memory system in the first power mode. (Kim, fig 1, “[0063] Furthermore, the supply of power to the remaining word line control circuits except for the current refresh address group and the subsequent refresh address group among the plurality of word line control circuits WL CC<l:16> may be disabled in response to the remaining deactivated group control signals.”; that “remaining word lines” WL5-WL16 may be disabled or deactivated for refresh operations duration in a “first power mode”).
Regarding claim 21, Kim teaches:
The non-transitory computer-readable medium of claim 19, wherein the instructions are further executable by the one or more processors to: determine whether a second duration satisfies a threshold based at least in part on receiving power at the first voltage rail, (Kim, fig 1, “[0108] At this time, the GROUP MANAGEMENT CIRCUIT 14 may generate the N current group signals WGCl<l:4> corresponding to the N refresh address groups, respectively, and generate the N subsequent group signals WGC2<1:4> by signal-shifting the N current group signals WGCl <1:4>.”; a timing scheme with at least a first duration of self-refresh for a first bank of word lines is activated. Note: as described in applicant’s specification, “a second duration satisfies a threshold” can be interpreted as counting a number of clock cycles for a self-refresh operation).
wherein perform the self-refresh operation of the memory system is based at least in part on determining that the second duration satisfies the threshold. (Kim, fig 8, “[0152] Before a first refresh address RADD is generated after the entry into the self-refresh section SELF-REFRESH, the first group control signal WC<l> of the four group control signals WC<l:4> may be activated and the remaining group control signals WC<2:4> may be deactivated (1000). [0153] Furthermore, since the four subsequent group signals WGC2<1:4> may be generated by signal-shifting the four current group signals WGCl<l:4>, the first subsequent group signal WGC2<1> of the four subsequent group signals WGC2<1:4> may be activated and the remaining subsequent group signals WGC2<2:4> may be deactivated (1000).”; a timing scheme with at least a second duration of self-refresh for a second bank of word lines is activated while other word lines are deactivated).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONALD H.B. BRASWELL whose telephone number is (469)295-9119. The examiner can normally be reached on 7-5 Central Time (Dallas).
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825
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