DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-4 and 6-27 are pending in this office action and presented for examination. Claims 1, 12, and 20 are newly amended; claim 5 is newly cancelled; and claims 22-27 are newly added by the response received June 9, 2026.
Examiner generally notes that deletions of dashes should be made with double brackets rather than strikethrough for purposes of clarity.
Drawings
The drawings are objected to because:
MPEP 608.02, section V, states that “[l]ead lines are required for each reference character except for those which indicate the surface or cross section on which they are placed. Such a reference character must be underlined to make it clear that a lead line has not been left out by mistake." In FIG. 4, reference characters 400 and 401 appear to be directed to a same surface area.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 6-11, 16-19, and 22-27 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 6 recites the limitation “the counter and the offset form a branch predictor entry for the fetch group” in line 3. Claim 1, upon which claim 6 is dependent, recites the limitation “modifying a hysteresis counter, separate from the counter, in response to an indication that the program was branched by a different branching instruction in the fetch group, wherein the hysteresis counter counts a number of times that one or more branching instructions other than the branching instruction have been taken; and associating the counter and the offset with the different branching instruction in response to the hysteresis counter reaching a threshold value” in lines 9-14. However, the original disclosure does not appear to provide support for the aforementioned limitation of claim 6 in the context of the aforementioned limitation of claim 1. For example, the original disclosure (e.g., paragraph [0040]) does not appear to provide support for the counter and the offset forming a branch predictor entry (i.e., the branch predictor entry consisting of the counter and the offset) for the fetch group in an embodiment which also entails a hysteresis counter.
Claim 7 recites the limitation “the counter and the offset form a branch predictor entry for the fetch group” in line 2. Claim 1, upon which claim 7 is dependent, recites the limitation “modifying a hysteresis counter, separate from the counter, in response to an indication that the program was branched by a different branching instruction in the fetch group, wherein the hysteresis counter counts a number of times that one or more branching instructions other than the branching instruction have been taken; and associating the counter and the offset with the different branching instruction in response to the hysteresis counter reaching a threshold value” in lines 9-14. However, the original disclosure does not appear to provide support for the aforementioned limitation of claim 7 in the context of the aforementioned limitation of claim 1. For example, the original disclosure (e.g., paragraph [0040]) does not appear to provide support for the counter and the offset forming a branch predictor entry (i.e., the branch predictor entry consisting of the counter and the offset) for the fetch group in an embodiment which also entails a hysteresis counter.
Claim 8 recites the limitation “the counter and the offset form a branch predictor entry for the fetch group” in line 3. Claim 1, upon which claim 8 is dependent, recites the limitation “modifying a hysteresis counter, separate from the counter, in response to an indication that the program was branched by a different branching instruction in the fetch group, wherein the hysteresis counter counts a number of times that one or more branching instructions other than the branching instruction have been taken; and associating the counter and the offset with the different branching instruction in response to the hysteresis counter reaching a threshold value” in lines 9-14. However, the original disclosure does not appear to provide support for the aforementioned limitation of claim 8 in the context of the aforementioned limitation of claim 1. For example, the original disclosure (e.g., paragraph [0040]) does not appear to provide support for the counter and the offset forming a branch predictor entry (i.e., the branch predictor entry consisting of the counter and the offset) for the fetch group in an embodiment which also entails a hysteresis counter.
Claim 8 recites the limitation “the branch predictor entry does not have any other counters” in line 5. Claim 1, upon which claim 8 is dependent, recites the limitation “modifying a hysteresis counter, separate from the counter, in response to an indication that the program was branched by a different branching instruction in the fetch group, wherein the hysteresis counter counts a number of times that one or more branching instructions other than the branching instruction have been taken; and associating the counter and the offset with the different branching instruction in response to the hysteresis counter reaching a threshold value” in lines 9-14. However, the original disclosure does not appear to provide support for the aforementioned limitation of claim 8 in the context of the aforementioned limitation of claim 1. For example, the original disclosure (e.g., paragraph [0040]) does not appear to provide support for the branch predictor entry not having any other counters in an embodiment which also entails a hysteresis counter.
Claim 9 recites the limitation “the counter and the offset form a branch predictor entry for the fetch group” in line 3. Claim 1, upon which claim 9 is dependent, recites the limitation “modifying a hysteresis counter, separate from the counter, in response to an indication that the program was branched by a different branching instruction in the fetch group, wherein the hysteresis counter counts a number of times that one or more branching instructions other than the branching instruction have been taken; and associating the counter and the offset with the different branching instruction in response to the hysteresis counter reaching a threshold value” in lines 9-14. However, the original disclosure does not appear to provide support for the aforementioned limitation of claim 9 in the context of the aforementioned limitation of claim 1. For example, the original disclosure (e.g., paragraph [0040]) does not appear to provide support for the counter and the offset forming a branch predictor entry (i.e., the branch predictor entry consisting of the counter and the offset) for the fetch group in an embodiment which also entails a hysteresis counter.
Claim 10 recites the limitation “the counter and the offset form a branch predictor entry for the fetch group” in line 2. Claim 1, upon which claim 10 is dependent, recites the limitation “modifying a hysteresis counter, separate from the counter, in response to an indication that the program was branched by a different branching instruction in the fetch group, wherein the hysteresis counter counts a number of times that one or more branching instructions other than the branching instruction have been taken; and associating the counter and the offset with the different branching instruction in response to the hysteresis counter reaching a threshold value” in lines 9-14. However, the original disclosure does not appear to provide support for the aforementioned limitation of claim 10 in the context of the aforementioned limitation of claim 1. For example, the original disclosure (e.g., paragraph [0040]) does not appear to provide support for the counter and the offset forming a branch predictor entry (i.e., the branch predictor entry consisting of the counter and the offset) for the fetch group in an embodiment which also entails a hysteresis counter.
Claim 11 recites the limitation “The method of claim 1, further comprising: associating a second counter and a second offset with a different branching instruction in the fetch group; receiving an indication that the program was branched by the different branching instruction in the fetch group; and incrementing the second counter in response to the indication” in lines 1-6. Claim 1, upon which claim 11 is dependent, recites the limitation “modifying a hysteresis counter, separate from the counter, in response to an indication that the program was branched by a different branching instruction in the fetch group, wherein the hysteresis counter counts a number of times that one or more branching instructions other than the branching instruction have been taken; and associating the counter and the offset with the different branching instruction in response to the hysteresis counter reaching a threshold value” in lines 9-14. However, the original disclosure does not appear to provide support for the aforementioned limitation of claim 11 in the context of the aforementioned limitation of claim 1. For example, the original disclosure (e.g., paragraph [0044]) does not appear to provide support for associating a second counter and a second offset with a different branching instruction in the fetch group; receiving an indication that the program was branched by the different branching instruction in the fetch group; and incrementing the second counter in response to the indication, in an embodiment which also entails a hysteresis counter.
Claim 16 recites the limitation “the counter and the offset form a branch predictor entry for the fetch group” in line 3. Claim 12, upon which claim 16 is dependent, recites the limitation “a hysteresis counter, separate from the counter, that is modified in response to an indication that the program was branched by a different branching instruction in the fetch group and that counts a number of times that one or more branching instructions other than the branching instruction have been taken, wherein the counter and the offset are associated with the different branching instruction in response to the hysteresis counter reaching a threshold value” in lines 9-14. However, the original disclosure does not appear to provide support for the aforementioned limitation of claim 16 in the context of the aforementioned limitation of claim 12. For example, the original disclosure (e.g., paragraph [0040]) does not appear to provide support for the counter and the offset forming a branch predictor entry (i.e., the branch predictor entry consisting of the counter and the offset) for the fetch group in an embodiment which also entails a hysteresis counter.
Claim 17 recites the limitation “the counter and the offset form a branch predictor entry for the fetch group” in line 2. Claim 12, upon which claim 17 is dependent, recites the limitation “a hysteresis counter, separate from the counter, that is modified in response to an indication that the program was branched by a different branching instruction in the fetch group and that counts a number of times that one or more branching instructions other than the branching instruction have been taken, wherein the counter and the offset are associated with the different branching instruction in response to the hysteresis counter reaching a threshold value” in lines 9-14. However, the original disclosure does not appear to provide support for the aforementioned limitation of claim 17 in the context of the aforementioned limitation of claim 12. For example, the original disclosure (e.g., paragraph [0040]) does not appear to provide support for the counter and the offset forming a branch predictor entry (i.e., the branch predictor entry consisting of the counter and the offset) for the fetch group in an embodiment which also entails a hysteresis counter.
Claim 18 recites the limitation “the counter and the offset form a branch predictor entry for the fetch group” in line 3. Claim 12, upon which claim 18 is dependent, recites the limitation “a hysteresis counter, separate from the counter, that is modified in response to an indication that the program was branched by a different branching instruction in the fetch group and that counts a number of times that one or more branching instructions other than the branching instruction have been taken, wherein the counter and the offset are associated with the different branching instruction in response to the hysteresis counter reaching a threshold value” in lines 9-14. However, the original disclosure does not appear to provide support for the aforementioned limitation of claim 18 in the context of the aforementioned limitation of claim 12. For example, the original disclosure (e.g., paragraph [0040]) does not appear to provide support for the counter and the offset forming a branch predictor entry (i.e., the branch predictor entry consisting of the counter and the offset) for the fetch group in an embodiment which also entails a hysteresis counter.
Claim 18 recites the limitation “the branch predictor entry does not have any other counters” in line 5. Claim 12, upon which claim 18 is dependent, recites the limitation “a hysteresis counter, separate from the counter, that is modified in response to an indication that the program was branched by a different branching instruction in the fetch group and that counts a number of times that one or more branching instructions other than the branching instruction have been taken, wherein the counter and the offset are associated with the different branching instruction in response to the hysteresis counter reaching a threshold value” in lines 9-14. However, the original disclosure does not appear to provide support for the aforementioned limitation of claim 18 in the context of the aforementioned limitation of claim 12. For example, the original disclosure (e.g., paragraph [0040]) does not appear to provide support for the branch predictor entry not having any other counters in an embodiment which also entails a hysteresis counter.
Claim 19 recites the limitation “the counter and the offset form a branch predictor entry for the fetch group” in line 3. Claim 12, upon which claim 19 is dependent, recites the limitation “a hysteresis counter, separate from the counter, that is modified in response to an indication that the program was branched by a different branching instruction in the fetch group and that counts a number of times that one or more branching instructions other than the branching instruction have been taken, wherein the counter and the offset are associated with the different branching instruction in response to the hysteresis counter reaching a threshold value” in lines 9-14. However, the original disclosure does not appear to provide support for the aforementioned limitation of claim 19 in the context of the aforementioned limitation of claim 12. For example, the original disclosure (e.g., paragraph [0040]) does not appear to provide support for the counter and the offset forming a branch predictor entry (i.e., the branch predictor entry consisting of the counter and the offset) for the fetch group in an embodiment which also entails a hysteresis counter.
Claim 22 recites the limitation “the threshold value is set independently for the fetch group relative to one or more other fetch groups of the program” in lines 1-2. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0021]) does not appear to provide support for the threshold value being set independently for the fetch group relative to just one other fetch group of the program, which is a scenario encompassed by the claim language in view of the “one or more” language.
Claim 23 is rejected for failing to alleviate the rejection of claim 22 above.
Claim 23 recites the limitation “the threshold value is computed dynamically for the fetch group based on one or more instructions in the fetch group” in lines 1-3. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0021]) does not appear to provide support for the threshold value being computed dynamically for the fetch group based on just one instruction in the fetch group, which is a scenario encompassed by the claim language in view of the “one or more” language.
Claim 24 recites the limitation “the threshold value is set independently for the fetch group relative to one or more other fetch groups of the program” in lines 1-2. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0021]) does not appear to provide support for the threshold value being set independently for the fetch group relative to just one other fetch group of the program, which is a scenario encompassed by the claim language in view of the “one or more” language.
Claim 25 is rejected for failing to alleviate the rejection of claim 24 above.
Claim 25 recites the limitation “the threshold value is computed dynamically for the fetch group based on one or more instructions in the fetch group” in lines 1-3. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0021]) does not appear to provide support for the threshold value being computed dynamically for the fetch group based on just one instruction in the fetch group, which is a scenario encompassed by the claim language in view of the “one or more” language.
Claim 26 recites the limitation “the threshold value is set independently for the fetch group relative to one or more other fetch groups of the program” in lines 1-3. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0021]) does not appear to provide support for the threshold value being set independently for the fetch group relative to just one other fetch group of the program, which is a scenario encompassed by the claim language in view of the “one or more” language.
Claim 27 is rejected for failing to alleviate the rejection of claim 26 above.
Claim 27 recites the limitation “the threshold value is computed dynamically for the fetch group based on one or more instructions in the fetch group” in lines 1-3. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0021]) does not appear to provide support for the threshold value being computed dynamically for the fetch group based on just one instruction in the fetch group, which is a scenario encompassed by the claim language in view of the “one or more” language.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-4, 11, 13-15, and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation “the branching instruction is associated with a value of the offset” in line 4. Claim 1, upon which claim 2 is dependent, recites the limitation “associating the counter and the offset with the different branching instruction” in lines 13-14. Therefore, it is indefinite as to whether the offset is associated with the branching instruction or the different branching instruction.
Claim 3 recites the limitation “incrementing the counter in response to the indication” in line 4. Claim 1, upon which claim 3 is dependent, recites the limitation “associating the counter and the offset with the different branching instruction in response to the hysteresis counter reaching a threshold value” in lines 13-14. Therefore, it is indefinite as to whether the incrementing step is being directed to the counter before, or after, being associated with the different branching instruction.
Claim 3 recites the limitation “the indication” in line 4. However, it is indefinite as to whether this limitation has antecedent basis to “an indication that the program was branched by a different branching instruction in the fetch group” in claim 1, lines 9-11, or “an indication that the program was branched by the branching instruction” in claim 3, line 2.
Claim 4 recites the limitation “an indication that the program was branched by a different branching instruction in the fetch group” in lines 2-3. However, it is indefinite as to whether this indication is the same as, or different from, “an indication that the program was branched by a different branching instruction in the fetch group” as recited in claim 1, lines 9-11.
Claim 4 recites the limitation “a different branching instruction in the fetch group” in lines 2-3. However, it is indefinite as to whether this different branching instruction in the same as, or different from, “a different branching instruction in the fetch group” as recited in claim 1, lines 10-11.
Claim 4 recites the limitation “lowering the counter in response to the indication” in line 4. Claim 1, upon which claim 4 is dependent, recites the limitation “associating the counter and the offset with the different branching instruction in response to the hysteresis counter reaching a threshold value” in lines 13-14. Therefore, it is indefinite as to whether the lowering step is being directed to the counter before, or after, being associated with the different branching instruction.
Claim 4 recites the limitation “the indication” in line 4. However, it is indefinite as to whether the antecedent basis for this limitation is “an indication” in claim 1, lines 9-10, or “an indication” in claim 4, line 2.
Claim 11 recites the limitation “a different branching instruction in the fetch group” in lines 2-3. However, it is indefinite as to whether this different branching instruction in the same as, or different from, “a different branching instruction in the fetch group” as recited in claim 1, lines 10-11.
Claim 11 recites the limitation “an indication that the program was branched by the different branching instruction in the fetch group” in lines 4-5. However, it is indefinite as to whether this indication is the same as, or different from, “an indication that the program was branched by a different branching instruction in the fetch group” as recited in claim 1, lines 9-11.
Claim 11 recites the limitation “the different branching instruction in the fetch group” in lines 4-5. However, it is indefinite as to whether the antecedent basis for this limitation is “a different branching instruction in the fetch group” in claim 1, lines 10-11, or “a different branching instruction in the fetch group” in claim 11, lines 2-3.
Claim 11 recites the limitation “the indication” in line 6. However, it is indefinite as to whether the antecedent basis for this limitation is “an indication” in claim 1, lines 9-10, or “an indication” in claim 11, line 4.
Claim 13 recites the limitation “the branching instruction is associated with a value of the offset” in line 4. Claim 12, upon which claim 13 is dependent, recites the limitation “the counter and the offset are associated with the different branching instruction” in lines 12-13. Therefore, it is indefinite as to whether the offset is associated with the branching instruction or the different branching instruction.
Claim 14 recites the limitation “the counter is incremented in response to an indication” in line 2. Claim 12, upon which claim 14 is dependent, recites the limitation “the counter and the offset are associated with the different branching instruction in response to the hysteresis counter reaching a threshold value” in lines 12-14. Therefore, it is indefinite as to whether the incrementing step is being directed to the counter before, or after, being associated with the different branching instruction.
Claim 15 recites the limitation “an indication that the program was branched by a different branching instruction in the fetch group” in lines 2-3. However, it is indefinite as to whether this indication is the same as, or different from, “an indication that the program was branched by a different branching instruction in the fetch group” as recited in claim 12, lines 9-11.
Claim 15 recites the limitation “a different branching instruction in the fetch group” in lines 2-3. However, it is indefinite as to whether this different branching instruction in the same as, or different from, “a different branching instruction in the fetch group” as recited in claim 12, lines 10-11.
Claim 15 recites the limitation “the counter is lowered in response to the indication” in line 4. Claim 12, upon which claim 15 is dependent, recites the limitation “the counter and the offset are associated with the different branching instruction in response to the hysteresis counter reaching a threshold value” in lines 12-14. Therefore, it is indefinite as to whether the lowering step is being directed to the counter before, or after, being associated with the different branching instruction.
Claim 15 recites the limitation “the indication” in line 4. However, it is indefinite as to whether the antecedent basis for this limitation is “an indication” in claim 12, lines 9-10, or “an indication” in claim 15, line 2.
Claim 15 recites the limitation “the offset is set to a second value associated with the different branching instruction” in line 5. Claim 12, upon which claim 15 is dependent, recites the limitation “the counter and the offset are associated with the different branching instruction in response to the hysteresis counter reaching a threshold value” in lines 12-14. Therefore, it is indefinite as to whether the setting step is being directed to the offset before, or after, being associated with the different branching instruction.
Claim 15 recites the limitation “the different branching instruction” in line 5. However, it is indefinite as to whether this limitation has antecedent basis to “a different branching instruction” in claim 12, line 10, or “a different branching instruction” in claim 15, lines 2-3.
Claim 21 recites the limitation “the branching instruction is associated with a value of the offset” in line 4. Claim 20, upon which claim 21 is dependent, recites the limitation “associating the counter and the offset with the different branching instruction” in line 15. Therefore, it is indefinite as to whether the offset is associated with the branching instruction or the different branching instruction.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6, 9, 11-16, 19, and 22-23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hoogerbrugge (US 20010020265 A1).
Consider claim 1, Hoogerbrugge discloses a method, in which each step is conducted by a branch prediction circuit ([0018], line 8, branch prediction unit) and an instruction fetch circuit ([0006], line 9, a bundle must be fetched; [0020], line 3, multiplexer 164) operating in combination in a computer processor ([0018], line 2, processor 10) that is executing a program ([0021], line 2, program of instructions), comprising: fetching a group of instructions ([0006], line 9, a bundle must be fetched; [0021], lines 3-4, number of commands; [0021], line 2, VLIW), in a fetch group ([0006], line 9, a bundle must be fetched; [0021], lines 3-4, number of commands; [0021], line 2, VLIW), from an instruction memory ([0018], line 5, instruction memory); associating a counter ([0012], lines 11-16, a saturating count of a number of executions of the branch command in which the branch is taken at that position. The state represents such a count only for the expected command, that is, only when there is a state transition to a different expected command a count for another command will start to become represented; [0013], lines 1-12, for example, the state for an instruction may represent that taking a branch as a result of a command at a certain position is expected. The state also represents a count of either 1 or 2 executions of that command where a branch is taken. If the branch is not taken when the instruction is executed and the state represents a count of 2, a transition will be made to a state where the command is still the expected command, but the count will go from 2 to 1. If the branch is not taken and the count is 1, a transition will be made to a state that represents that another branch command, if any, is the expectedly taken branch with a count of 1 for that other command; [0041], lines 5-6, one bit to represent whether there is a strong or a weak preference; [0041], line 9, more bits for the strength of the prediction; [0039], lines 1-12, if the branch history memory 160 stores information identifying a state that represents a strong preference for an outcome of the source instruction and that outcome occurs as a result of execution, the state remains unaffected. If a different outcome occurs and the state has a strong preference, a transition is made to the state with a weak preference for the same outcome as the original state with a strong preference. If the state represents a weak preference for an outcome of the source instruction and that outcome occurs as a result of execution, a transition occurs to the state with a strong preference for the same outcome as the original state with a weak preference; [0040], lines 6-7, information similar to the saturating count is represented only for the preferred outcome; alternatively, [0018], line 2, program counter) and an offset ([0041], lines 6-7, two bits to represent for which of the four possible outcomes there is a preference; [0038], lines 1-4, the diagram shows states for prediction of a "no-branch" outcome and for a taken outcome of a branch command from a first, second or third position in the source instruction respectively) with the fetch group ([0035], lines 4-6, branch history memory is an associative memory (e.g. fully associative, set associative or direct mapped), that can be accessed using the address of the source instruction; [0006], line 9, a bundle must be fetched; [0021], lines 3-4, number of commands; [0021], line 2, VLIW); predicting, using the counter and the offset, that a branching instruction in the fetch group will be used to branch the program ([0025], lines 4-12, the branch history information represents statistical information about the frequency with which the one or more branch commands from the instruction have led to a change in the program counter 12 before. Selection unit 161 uses this information to generate a decision whether a taken branch should be predicted and which of the branch commands in the instruction is the taken branch whose target address will affect the program counter 12); and prefetching at least one instruction indicated by the branching instruction ([0024], lines 1-6, the branch prediction unit 16 caters for this problem by predicting which instructions should be executed after an instruction that contains one or more branch commands, before the processor 10 has actually been able to instruct the program counter 12 about the result of the branch commands); modifying a hysteresis counter, separate from the counter, in response to an indication that the program was branched by a different branching instruction in the fetch group, wherein the hysteresis counter counts a number of times that one or more branching instructions other than the branching instruction have been taken; and associating the counter and the offset with the different branching instruction in response to the hysteresis counter reaching a threshold value (Examiner notes that these limitations are contingent limitations. The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met — see MPEP 2111.04; alternatively, in the alternative mapping of the counter to a program counter above, [0012], lines 11-16, a saturating count of a number of executions of the branch command in which the branch is taken at that position. The state represents such a count only for the expected command, that is, only when there is a state transition to a different expected command a count for another command will start to become represented; [0013], lines 1-12, for example, the state for an instruction may represent that taking a branch as a result of a command at a certain position is expected. The state also represents a count of either 1 or 2 executions of that command where a branch is taken. If the branch is not taken when the instruction is executed and the state represents a count of 2, a transition will be made to a state where the command is still the expected command, but the count will go from 2 to 1. If the branch is not taken and the count is 1, a transition will be made to a state that represents that another branch command, if any, is the expectedly taken branch with a count of 1 for that other command; [0041], lines 5-6, one bit to represent whether there is a strong or a weak preference; [0041], line 9, more bits for the strength of the prediction; [0039], lines 1-12, if the branch history memory 160 stores information identifying a state that represents a strong preference for an outcome of the source instruction and that outcome occurs as a result of execution, the state remains unaffected. If a different outcome occurs and the state has a strong preference, a transition is made to the state with a weak preference for the same outcome as the original state with a strong preference. If the state represents a weak preference for an outcome of the source instruction and that outcome occurs as a result of execution, a transition occurs to the state with a strong preference for the same outcome as the original state with a weak preference; [0040], lines 6-7, information similar to the saturating count is represented only for the preferred outcome).
Consider claim 2, Hoogerbrugge discloses the method of claim 1 (see above), wherein: the offset comprises sufficient bits to represent each instruction in the fetch group ([0041], lines 6-7, two bits to represent for which of the four possible outcomes there is a preference; [0038], lines 1-4, the diagram shows states for prediction of a "no-branch" outcome and for a taken outcome of a branch command from a first, second or third position in the source instruction respectively); and the branching instruction is associated with a value of the offset ([0041], lines 6-7, two bits to represent for which of the four possible outcomes there is a preference; [0038], lines 1-4, the diagram shows states for prediction of a "no-branch" outcome and for a taken outcome of a branch command from a first, second or third position in the source instruction respectively).
Consider claim 3, Hoogerbrugge discloses the method of claim 1 (see above), further comprising: receiving an indication that the program was branched by the branching instruction; and incrementing the counter in response to the indication ([0012], lines 11-13, a saturating count of a number of executions of the branch command in which the branch is taken at that position; [0039], lines 8-12, if the state represents a weak preference for an outcome of the source instruction and that outcome occurs as a result of execution, a transition occurs to the state with a strong preference for the same outcome as the original state with a weak preference; alternatively, [0018], line 2, program counter; examiner notes that a program counter is incremented in response to a branch target instruction not being a branch itself).
Consider claim 4, Hoogerbrugge discloses the method of claim 1 (see above), further comprising: receiving an indication that the program was branched by a different branching instruction in the fetch group; and lowering the counter in response to the indication ([0013], lines 5-8, if the branch is not taken when the instruction is executed and the state represents a count of 2, a transition will be made to a state where the command is still the expected command, but the count will go from 2 to 1; [0039], lines 5-8, if a different outcome occurs and the state has a strong preference, a transition is made to the state with a weak preference for the same outcome as the original state with a strong preference; alternatively, [0018], line 2, program counter; examiner notes that a branch backwards entails a lowering of the program counter).
Consider claim 6, Hoogerbrugge discloses the method of claim 1 (see above), wherein: the fetch group has a number of instructions that is at least 4 ([0002], lines 1-3, VLIW processors have instructions that are made up of at least two commands for simultaneous execution by the processor); the counter and the offset form a branch predictor entry for the fetch group ([0035], lines 1-3, branch history memory 160 stores information about a state that represents statistical information about previous executions of the source instruction; [0035], lines 4-6, branch history memory is an associative memory (e.g. fully associative, set associative or direct mapped), that can be accessed using the address of the source instruction; [0006], line 9, a bundle must be fetched; [0021], lines 3-4, number of commands; [0021], line 2, VLIW; alternatively, [0011], lines 4-8, the address of an instruction is used as an index to find the set in which the target is to be found. The branch target of a command in the instruction is stored in association with a tag that contains an identification of the position of the command); the offset is less than or equal to a number of bits required to represent the number of instructions ([0041], lines 6-7, two bits to represent for which of the four possible outcomes there is a preference; [0038], lines 1-4, the diagram shows states for prediction of a "no-branch" outcome and for a taken outcome of a branch command from a first, second or third position in the source instruction respectively; [0002], lines 1-3, VLIW processors have instructions that are made up of at least two commands for simultaneous execution by the processor); and the branch predictor entry is less than or equal to 9 bits ([0041], lines 3-11, in the example of FIG. 3, 3-bit labels may be used. One way of assigning these labels is to use one bit to represent whether there is a strong or a weak preference and two bits to represent for which of the four possible outcomes there is a preference. Of course, with other state diagrams other assignments may be used, using more bits for the strength of the preference and an appropriate number of bits to distinguish the preferred outcome; [0002], lines 1-3, VLIW processors have instructions that are made up of at least two commands for simultaneous execution by the processor).
Consider claim 9, Hoogerbrugge discloses the method of claim 1 (see above), wherein: the fetch group has a number of instructions that is at least 16 ([0002], lines 1-3, VLIW processors have instructions that are made up of at least two commands for simultaneous execution by the processor); the counter and the offset form a branch predictor entry for the fetch group ([0035], lines 1-3, branch history memory 160 stores information about a state that represents statistical information about previous executions of the source instruction; [0035], lines 4-6, branch history memory is an associative memory (e.g. fully associative, set associative or direct mapped), that can be accessed using the address of the source instruction; [0006], line 9, a bundle must be fetched; [0021], lines 3-4, number of commands; [0021], line 2, VLIW; alternatively, [0011], lines 4-8, the address of an instruction is used as an index to find the set in which the target is to be found. The branch target of a command in the instruction is stored in association with a tag that contains an identification of the position of the command); the offset is less than or equal to a number of bits needed to represent the number of instructions ([0041], lines 6-7, two bits to represent for which of the four possible outcomes there is a preference; [0038], lines 1-4, the diagram shows states for prediction of a "no-branch" outcome and for a taken outcome of a branch command from a first, second or third position in the source instruction respectively; [0002], lines 1-3, VLIW processors have instructions that are made up of at least two commands for simultaneous execution by the processor); and the branch predictor entry is less than or equal to 9 bits ([0041], lines 3-11, in the example of FIG. 3, 3-bit labels may be used. One way of assigning these labels is to use one bit to represent whether there is a strong or a weak preference and two bits to represent for which of the four possible outcomes there is a preference. Of course, with other state diagrams other assignments may be used, using more bits for the strength of the preference and an appropriate number of bits to distinguish the preferred outcome; [0002], lines 1-3, VLIW processors have instructions that are made up of at least two commands for simultaneous execution by the processor).
Consider claim 11, Hoogerbrugge discloses the method of claim 1 (see above), further comprising: associating a second counter ([0012], lines 11-16, a saturating count of a number of executions of the branch command in which the branch is taken at that position. The state represents such a count only for the expected command, that is, only when there is a state transition to a different expected command a count for another command will start to become represented; [0013], lines 1-12, for example, the state for an instruction may represent that taking a branch as a result of a command at a certain position is expected. The state also represents a count of either 1 or 2 executions of that command where a branch is taken. If the branch is not taken when the instruction is executed and the state represents a count of 2, a transition will be made to a state where the command is still the expected command, but the count will go from 2 to 1. If the branch is not taken and the count is 1, a transition will be made to a state that represents that another branch command, if any, is the expectedly taken branch with a count of 1 for that other command; [0041], lines 5-6, one bit to represent whether there is a strong or a weak preference; [0041], line 9, more bits for the strength of the prediction; [0039], lines 1-12, if the branch history memory 160 stores information identifying a state that represents a strong preference for an outcome of the source instruction and that outcome occurs as a result of execution, the state remains unaffected. If a different outcome occurs and the state has a strong preference, a transition is made to the state with a weak preference for the same outcome as the original state with a strong preference. If the state represents a weak preference for an outcome of the source instruction and that outcome occurs as a result of execution, a transition occurs to the state with a strong preference for the same outcome as the original state with a weak preference; [0040], lines 6-7, information similar to the saturating count is represented only for the preferred outcome) and a second offset with a different branching instruction ([0041], lines 6-7, two bits to represent for which of the four possible outcomes there is a preference; [0038], lines 1-4, the diagram shows states for prediction of a "no-branch" outcome and for a taken outcome of a branch command from a first, second or third position in the source instruction respectively) in the fetch group ([0035], lines 4-6, branch history memory is an associative memory (e.g. fully associative, set associative or direct mapped), that can be accessed using the address of the source instruction; [0006], line 9, a bundle must be fetched; [0021], lines 3-4, number of commands; [0021], line 2, VLIW); receiving an indication that the program was branched by the different branching instruction in the fetch group; and incrementing the second counter in response to the indication ([0012], lines 11-13, a saturating count of a number of executions of the branch command in which the branch is taken at that position; [0039], lines 8-12, if the state represents a weak preference for an outcome of the source instruction and that outcome occurs as a result of execution, a transition occurs to the state with a strong preference for the same outcome as the original state with a weak preference).
Consider claim 12, Hoogerbrugge discloses a processor ([0018], line 2, processor 10) comprising: a branch prediction circuit ([0018], line 8, branch prediction unit); an instruction fetch circuit ([0006], line 9, a bundle must be fetched; [0020], line 3, multiplexer 164), wherein the instruction fetch circuit fetches a group of instructions ([0006], line 9, a bundle must be fetched; [0021], lines 3-4, number of commands; [0021], line 2, VLIW), in a fetch group ([0006], line 9, a bundle must be fetched; [0021], lines 3-4, number of commands; [0021], line 2, VLIW), from an instruction memory ([0018], line 5, instruction memory); a counter ([0018], line 2, program counter) and an offset ([0041], lines 6-7, two bits to represent for which of the four possible outcomes there is a preference; [0038], lines 1-4, the diagram shows states for prediction of a "no-branch" outcome and for a taken outcome of a branch command from a first, second or third position in the source instruction respectively) associated with the fetch group ([0035], lines 4-6, branch history memory is an associative memory (e.g. fully associative, set associative or direct mapped), that can be accessed using the address of the source instruction; [0006], line 9, a bundle must be fetched; [0021], lines 3-4, number of commands; [0021], line 2, VLIW), wherein the counter and the offset are used to predict that a branching instruction in the fetch group will be used to branch a program ([0025], lines 4-12, the branch history information represents statistical information about the frequency with which the one or more branch commands from the instruction have led to a change in the program counter 12 before. Selection unit 161 uses this information to generate a decision whether a taken branch should be predicted and which of the branch commands in the instruction is the taken branch whose target address will affect the program counter 12; Figure 1, connection between program counter 12 and branch prediction unit 16), and at least one instruction indicated by the branching instruction is prefetched ([0024], lines 1-6, the branch prediction unit 16 caters for this problem by predicting which instructions should be executed after an instruction that contains one or more branch commands, before the processor 10 has actually been able to instruct the program counter 12 about the result of the branch commands); and a hysteresis counter, separate from the counter, that is modified in response to an indication that the program was branched by a different branching instruction in the fetch group and that counts a number of times that one or more branching instructions other than the branching instruction have been taken, wherein the counter and the offset are associated with the different branching instruction in response to the hysteresis counter reaching a threshold value ([0012], lines 11-16, a saturating count of a number of executions of the branch command in which the branch is taken at that position. The state represents such a count only for the expected command, that is, only when there is a state transition to a different expected command a count for another command will start to become represented; [0013], lines 1-12, for example, the state for an instruction may represent that taking a branch as a result of a command at a certain position is expected. The state also represents a count of either 1 or 2 executions of that command where a branch is taken. If the branch is not taken when the instruction is executed and the state represents a count of 2, a transition will be made to a state where the command is still the expected command, but the count will go from 2 to 1. If the branch is not taken and the count is 1, a transition will be made to a state that represents that another branch command, if any, is the expectedly taken branch with a count of 1 for that other command; [0041], lines 5-6, one bit to represent whether there is a strong or a weak preference; [0041], line 9, more bits for the strength of the prediction; [0039], lines 1-12, if the branch history memory 160 stores information identifying a state that represents a strong preference for an outcome of the source instruction and that outcome occurs as a result of execution, the state remains unaffected. If a different outcome occurs and the state has a strong preference, a transition is made to the state with a weak preference for the same outcome as the original state with a strong preference. If the state represents a weak preference for an outcome of the source instruction and that outcome occurs as a result of execution, a transition occurs to the state with a strong preference for the same outcome as the original state with a weak preference; [0040], lines 6-7, information similar to the saturating count is represented only for the preferred outcome).
Consider claim 13, Hoogerbrugge discloses the processor of claim 12 (see above), wherein: the offset comprises sufficient bits to represent each instruction in the fetch group ([0041], lines 6-7, two bits to represent for which of the four possible outcomes there is a preference; [0038], lines 1-4, the diagram shows states for prediction of a "no-branch" outcome and for a taken outcome of a branch command from a first, second or third position in the source instruction respectively); and the branching instruction is associated with a value of the offset ([0041], lines 6-7, two bits to represent for which of the four possible outcomes there is a preference; [0038], lines 1-4, the diagram shows states for prediction of a "no-branch" outcome and for a taken outcome of a branch command from a first, second or third position in the source instruction respectively).
Consider claim 14, Hoogerbrugge discloses the processor of claim 12 (see above), wherein: the counter is incremented in response to an indication that the program was branched by the branching instruction ([0018], line 2, program counter; examiner notes that a program counter is incremented in response to a branch target instruction not being a branch itself).
Consider claim 15, Hoogerbrugge discloses the processor of claim 12 (see above), wherein: the processor receives an indication that the program was branched by a different branching instruction in the fetch group; the counter is lowered in response to the indication ([0018], line 2, program counter; examiner notes that a branch backwards entails a lowering of the program counter); and the offset is set to a second value associated with the different branching instruction ([0013], lines 8-12, if the branch is not taken and the count is 1, a transition will be made to a state that represents that another branch command, if any, is the expectedly taken branch with a count of 1 for that other command).
Consider claim 16, Hoogerbrugge discloses the processor of claim 12 (see above), wherein: the fetch group has a number of instructions that is at least 16 ([0002], lines 1-3, VLIW processors have instructions that are made up of at least two commands for simultaneous execution by the processor); the counter and the offset form a branch predictor entry for the fetch group ([0035], lines 1-3, branch history memory 160 stores information about a state that represents statistical information about previous executions of the source instruction; [0035], lines 4-6, branch history memory is an associative memory (e.g. fully associative, set associative or direct mapped), that can be accessed using the address of the source instruction; [0006], line 9, a bundle must be fetched; [0021], lines 3-4, number of commands; [0021], line 2, VLIW; [0011], lines 4-8, the address of an instruction is used as an index to find the set in which the target is to be found. The branch target of a command in the instruction is stored in association with a tag that contains an identification of the position of the command); the offset is less than or equal to a number of bits required to represent the number of instructions ([0041], lines 6-7, two bits to represent for which of the four possible outcomes there is a preference; [0038], lines 1-4, the diagram shows states for prediction of a "no-branch" outcome and for a taken outcome of a branch command from a first, second or third position in the source instruction respectively; [0002], lines 1-3, VLIW processors have instructions that are made up of at least two commands for simultaneous execution by the processor); and the branch predictor entry is less than or equal to 9 bits ([0041], lines 3-11, in the example of FIG. 3, 3-bit labels may be used. One way of assigning these labels is to use one bit to represent whether there is a strong or a weak preference and two bits to represent for which of the four possible outcomes there is a preference. Of course, with other state diagrams other assignments may be used, using more bits for the strength of the preference and an appropriate number of bits to distinguish the preferred outcome; [0002], lines 1-3, VLIW processors have instructions that are made up of at least two commands for simultaneous execution by the processor).
Consider claim 19, Hoogerbrugge discloses the processor of claim 12 (see above), wherein: the fetch group has a number of instructions that is at least 16 ([0002], lines 1-3, VLIW processors have instructions that are made up of at least two commands for simultaneous execution by the processor); the counter and the offset form a branch predictor entry for the fetch group ([0035], lines 1-3, branch history memory 160 stores information about a state that represents statistical information about previous executions of the source instruction; [0035], lines 4-6, branch history memory is an associative memory (e.g. fully associative, set associative or direct mapped), that can be accessed using the address of the source instruction; [0006], line 9, a bundle must be fetched; [0021], lines 3-4, number of commands; [0021], line 2, VLIW; [0011], lines 4-8, the address of an instruction is used as an index to find the set in which the target is to be found. The branch target of a command in the instruction is stored in association with a tag that contains an identification of the position of the command); the offset is less than or equal to a number of bits needed to represent the number of instructions ([0041], lines 6-7, two bits to represent for which of the four possible outcomes there is a preference; [0038], lines 1-4, the diagram shows states for prediction of a "no-branch" outcome and for a taken outcome of a branch command from a first, second or third position in the source instruction respectively; [0002], lines 1-3, VLIW processors have instructions that are made up of at least two commands for simultaneous execution by the processor); and the branch predictor entry is less than or equal to 9 bits ([0041], lines 3-11, in the example of FIG. 3, 3-bit labels may be used. One way of assigning these labels is to use one bit to represent whether there is a strong or a weak preference and two bits to represent for which of the four possible outcomes there is a preference. Of course, with other state diagrams other assignments may be used, using more bits for the strength of the preference and an appropriate number of bits to distinguish the preferred outcome; [0002], lines 1-3, VLIW processors have instructions that are made up of at least two commands for simultaneous execution by the processor).
Consider claim 22, Hoogerbrugge discloses the method of claim 1, wherein the threshold value is set independently for the fetch group relative to one or more other fetch groups of the program (Examiner notes that this limitation further limits a contingent limitation; see the rejection of claim 1).
Consider claim 23, Hoogerbrugge discloses method of claim 22, wherein the threshold value is computed dynamically for the fetch group based on one or more instructions in the fetch group (Examiner notes that this limitation further limits a contingent limitation; see the rejection of claim 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7, 10, 17, and 20-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hoogerbrugge (in the case of claims 7, 10, and 17, as applied to claims 1 and 12 above), and further in view of Navada (US 20170322810 A1)
Consider claim 7, Hoogerbrugge discloses the method of claim 1 (see above), wherein: the counter and the offset form a branch predictor entry for the fetch group in a table of the branch prediction circuit ([0035], lines 1-3, branch history memory 160 stores information about a state that represents statistical information about previous executions of the source instruction; [0035], lines 4-6, branch history memory is an associative memory (e.g. fully associative, set associative or direct mapped), that can be accessed using the address of the source instruction; [0006], line 9, a bundle must be fetched; [0021], lines 3-4, number of commands; [0021], line 2, VLIW; alternatively, [0011], lines 4-8, the address of an instruction is used as an index to find the set in which the target is to be found. The branch target of a command in the instruction is stored in association with a tag that contains an identification of the position of the command).
However, Hoogerbrugge does not disclose that the branch predictor entry is in a tagged geometric history length table of the branch prediction circuit.
On the other hand, Navada discloses a branch predictor entry is in a tagged geometric history length table of a branch prediction circuit ([0005], lines 4-7, TAGE predictors are gaining popularity for their ability to make predictions of increased accuracy by taking into account contexts and history associated with branch instructions).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Navada with the invention of Hoogerbrugge in order to increase prediction accuracy.
Consider claim 10, Hoogerbrugge discloses the method of claim 1 (see above), wherein: the counter and the offset form a branch predictor entry for the fetch group in a table of the branch prediction circuit ([0035], lines 1-3, branch history memory 160 stores information about a state that represents statistical information about previous executions of the source instruction; [0035], lines 4-6, branch history memory is an associative memory (e.g. fully associative, set associative or direct mapped), that can be accessed using the address of the source instruction; [0006], line 9, a bundle must be fetched; [0021], lines 3-4, number of commands; [0021], line 2, VLIW; alternatively, [0011], lines 4-8, the address of an instruction is used as an index to find the set in which the target is to be found. The branch target of a command in the instruction is stored in association with a tag that contains an identification of the position of the command); the table includes a set of branch predictor entries; and each branch predictor entry in the set of branch predictor entries is associated with a different fetch group of the program ([0035], lines 4-6, branch history memory is an associative memory (e.g. fully associative, set associative or direct mapped), that can be accessed using the address of the source instruction).
However, Hoogerbrugge does not disclose that the branch predictor entry is in a tagged geometric history length table of the branch prediction circuit.
On the other hand, Navada discloses a branch predictor entry is in a tagged geometric history length table of a branch prediction circuit ([0005], lines 4-7, TAGE predictors are gaining popularity for their ability to make predictions of increased accuracy by taking into account contexts and history associated with branch instructions).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Navada with the invention of Hoogerbrugge in order to increase prediction accuracy.
Consider claim 17, Hoogerbrugge discloses the processor of claim 12 (see above), wherein: the counter and the offset form a branch predictor entry for the fetch group in a table of the branch prediction circuit ([0035], lines 1-3, branch history memory 160 stores information about a state that represents statistical information about previous executions of the source instruction; [0035], lines 4-6, branch history memory is an associative memory (e.g. fully associative, set associative or direct mapped), that can be accessed using the address of the source instruction; [0006], line 9, a bundle must be fetched; [0021], lines 3-4, number of commands; [0021], line 2, VLIW; [0011], lines 4-8, the address of an instruction is used as an index to find the set in which the target is to be found. The branch target of a command in the instruction is stored in association with a tag that contains an identification of the position of the command).
However, Hoogerbrugge does not disclose that the branch predictor entry is in a tagged geometric history length table of the branch prediction circuit.
On the other hand, Navada discloses a branch predictor entry is in a tagged geometric history length table of a branch prediction circuit ([0005], lines 4-7, TAGE predictors are gaining popularity for their ability to make predictions of increased accuracy by taking into account contexts and history associated with branch instructions).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Navada with the invention of Hoogerbrugge in order to increase prediction accuracy.
Consider claim 20, Hoogerbrugge discloses a method in which each step is conducted by a branch prediction circuit ([0018], line 8, branch prediction unit) and an instruction fetch circuit ([0006], line 9, a bundle must be fetched; [0020], line 3, multiplexer 164) operating in combination in a computer processor ([0018], line 2, processor 10) that is executing a program ([0021], line 2, program of instructions), comprising: fetching a group of instructions ([0006], line 9, a bundle must be fetched; [0021], lines 3-4, number of commands; [0021], line 2, VLIW), in a fetch group ([0006], line 9, a bundle must be fetched; [0021], lines 3-4, number of commands; [0021], line 2, VLIW), from an instruction memory ([0018], line 5, instruction memory); associating a counter ([0018], line 2, program counter) and an offset ([0041], lines 6-7, two bits to represent for which of the four possible outcomes there is a preference; [0038], lines 1-4, the diagram shows states for prediction of a "no-branch" outcome and for a taken outcome of a branch command from a first, second or third position in the source instruction respectively) with the fetch group ([0035], lines 4-6, branch history memory is an associative memory (e.g. fully associative, set associative or direct mapped), that can be accessed using the address of the source instruction; [0006], line 9, a bundle must be fetched; [0021], lines 3-4, number of commands; [0021], line 2, VLIW); predicting, using the counter and the offset, that a branching instruction in the fetch group will be used to branch the program ([0025], lines 4-12, the branch history information represents statistical information about the frequency with which the one or more branch commands from the instruction have led to a change in the program counter 12 before. Selection unit 161 uses this information to generate a decision whether a taken branch should be predicted and which of the branch commands in the instruction is the taken branch whose target address will affect the program counter 12); and prefetching at least one instruction indicated by the branching instruction ([0024], lines 1-6, the branch prediction unit 16 caters for this problem by predicting which instructions should be executed after an instruction that contains one or more branch commands, before the processor 10 has actually been able to instruct the program counter 12 about the result of the branch commands); and modifying a hysteresis counter, separate from the counter, in response to an indication that the program was branched by a different branching instruction in the fetch group, wherein the hysteresis counter counts a number of times that one or more branching instructions other than the branching instruction have been taken; and associating the counter and the offset with the different branching instruction in response to the hysteresis counter reaching a threshold value ([0012], lines 11-16, a saturating count of a number of executions of the branch command in which the branch is taken at that position. The state represents such a count only for the expected command, that is, only when there is a state transition to a different expected command a count for another command will start to become represented; [0013], lines 1-12, for example, the state for an instruction may represent that taking a branch as a result of a command at a certain position is expected. The state also represents a count of either 1 or 2 executions of that command where a branch is taken. If the branch is not taken when the instruction is executed and the state represents a count of 2, a transition will be made to a state where the command is still the expected command, but the count will go from 2 to 1. If the branch is not taken and the count is 1, a transition will be made to a state that represents that another branch command, if any, is the expectedly taken branch with a count of 1 for that other command; [0041], lines 5-6, one bit to represent whether there is a strong or a weak preference; [0041], line 9, more bits for the strength of the prediction; [0039], lines 1-12, if the branch history memory 160 stores information identifying a state that represents a strong preference for an outcome of the source instruction and that outcome occurs as a result of execution, the state remains unaffected. If a different outcome occurs and the state has a strong preference, a transition is made to the state with a weak preference for the same outcome as the original state with a strong preference. If the state represents a weak preference for an outcome of the source instruction and that outcome occurs as a result of execution, a transition occurs to the state with a strong preference for the same outcome as the original state with a weak preference; [0040], lines 6-7, information similar to the saturating count is represented only for the preferred outcome).
However, Hoogerbrugge does not explicitly disclose a non-transitory computer-readable medium storing instructions, which when executed by a processor cause the processor to conduct the aforementioned method.
On the other hand, Navada discloses a non-transitory computer-readable medium storing instructions, which when executed by a processor cause the processor to conduct a method ([0015], lines 1-4, yet another exemplary aspect is directed to a non-transitory computer readable storage medium comprising code, which, when executed by a processor, causes the processor to perform operations).
It would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to combine the teaching of Navada with the invention of Hoogerbrugge in order to increase flexibility relative to a fully hardware approach. Alternatively, this modification merely entails combining prior art elements (the prior art elements of Hoogerbrugge as cited above, and Navada’s explicit teaching of a non-transitory computer-readable medium embodiment) according to known methods (Examiner submits that the general use of a non-transitory computer-readable medium to implement a method was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention) to yield predictable results (the invention of Hoogerbrugge, implemented via a non-transitory computer-readable medium), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
Consider claim 21, the overall combination entails discloses the non-transitory computer-readable medium of claim 20 (see above), wherein: the offset comprises sufficient bits to represent each instruction in the fetch group (Hoogerbrugge, [0041], lines 6-7, two bits to represent for which of the four possible outcomes there is a preference; [0038], lines 1-4, the diagram shows states for prediction of a "no-branch" outcome and for a taken outcome of a branch command from a first, second or third position in the source instruction respectively); and the branching instruction is associated with a value of the offset ([0041], lines 6-7, two bits to represent for which of the four possible outcomes there is a preference; [0038], lines 1-4, the diagram shows states for prediction of a "no-branch" outcome and for a taken outcome of a branch command from a first, second or third position in the source instruction respectively).
Claim(s) 8 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hoogerbrugge as applied to claims 1 and 12 above, and further in view of Navada (US 20170322810 A1) and Kumar et al. (Kumar) (US 20220302917 A1)
Consider claim 8, Hoogerbrugge discloses the method of claim 1 (see above), wherein: the counter and the offset form a branch predictor entry for the fetch group in a table of the branch prediction circuit ([0035], lines 1-3, branch history memory 160 stores information about a state that represents statistical information about previous executions of the source instruction; [0035], lines 4-6, branch history memory is an associative memory (e.g. fully associative, set associative or direct mapped), that can be accessed using the address of the source instruction; [0006], line 9, a bundle must be fetched; [0021], lines 3-4, number of commands; [0021], line 2, VLIW; alternatively, [0011], lines 4-8, the address of an instruction is used as an index to find the set in which the target is to be found. The branch target of a command in the instruction is stored in association with a tag that contains an identification of the position of the command); and the branch predictor entry does not have any other counters ([0040], lines 6-7, information similar to the saturating count is represented only for the preferred outcome).
However, Hoogerbrugge does not disclose that the branch predictor entry is in a tagged geometric history length table of the branch prediction circuit. Hoogerbrugge also does not disclose the computer processor is a RISC-V processor with C-extension support.
On the other hand, Navada discloses a branch predictor entry is in a tagged geometric history length table of a branch prediction circuit ([0005], lines 4-7, TAGE predictors are gaining popularity for their ability to make predictions of increased accuracy by taking into account contexts and history associated with branch instructions).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Navada with the invention of Hoogerbrugge in order to increase prediction accuracy.
However, the combination thus far does not entail that the computer processor is a RISC-V processor with C-extension support.
On the other hand, Kumar discloses a computer processor that is a RISC-V processor ([0043], line 4, RISC-V) with C-extension support ([0099], line 3, RISC-V c-extension).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Kumar with the combination of Hoogerbrugge and Navada in order to increase efficiency (Hoogerbrugge, [0007], line 1) for RISC-V processors with C-extension support in particular, and in order to avoid restrictions or licensing issues (Kumar, [0043], lines 5-6).
Consider claim 18, Hoogerbrugge discloses the processor of claim 12 (see above), wherein: the counter and the offset form a branch predictor entry for the fetch group in a table of the branch prediction circuit ([0035], lines 1-3, branch history memory 160 stores information about a state that represents statistical information about previous executions of the source instruction; [0035], lines 4-6, branch history memory is an associative memory (e.g. fully associative, set associative or direct mapped), that can be accessed using the address of the source instruction; [0006], line 9, a bundle must be fetched; [0021], lines 3-4, number of commands; [0021], line 2, VLIW; [0011], lines 4-8, the address of an instruction is used as an index to find the set in which the target is to be found. The branch target of a command in the instruction is stored in association with a tag that contains an identification of the position of the command); and the branch predictor entry does not have any other counters ([0040], lines 6-7, information similar to the saturating count is represented only for the preferred outcome).
However, Hoogerbrugge does not disclose that the branch predictor entry is in a tagged geometric history length table of the branch prediction circuit. Hoogerbrugge also does not disclose the processor is a RISC-V processor with C-extension support.
On the other hand, Navada discloses a branch predictor entry is in a tagged geometric history length table of a branch prediction circuit ([0005], lines 4-7, TAGE predictors are gaining popularity for their ability to make predictions of increased accuracy by taking into account contexts and history associated with branch instructions).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Navada with the invention of Hoogerbrugge in order to increase prediction accuracy.
However, the combination thus far does not entail that the processor is a RISC-V processor with C-extension support.
On the other hand, Kumar discloses a processor that is a RISC-V processor ([0043], line 4, RISC-V) with C-extension support ([0099], line 3, RISC-V c-extension).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Kumar with the combination of Hoogerbrugge and Navada in order to increase efficiency (Hoogerbrugge, [0007], line 1) for RISC-V processors with C-extension support in particular, and in order to avoid restrictions or licensing issues (Kumar, [0043], lines 5-6).
Response to Arguments
Examiner greatly appreciates Applicant’s citations, across pages 14-15 of the remarks, of both paragraphs of the instant specification and specific portions within those paragraphs.
Applicant on page 18 argues: “In view of the foregoing, Applicant respectfully submits that the specification has been amended to address each of the Examiner's objections without the introduction of new matter, and requests that the objections to the specification be withdrawn.”
In view of the aforementioned amendments, the previously presented objections are withdrawn. Examiner greatly appreciates the remarks explaining the amendments to the specification across pages 15-18.
Applicant on page 18 argues: “Applicant respectfully submits that the replacement sheets resolve each of the objections to the drawings and requests that the objections be withdrawn.”
In view of the aforementioned replacement sheets, the previously presented objections to the drawings are withdrawn.
Applicant on page 20 argues: ‘Notably, in rejecting now-canceled claim 5 (which recited a hysteresis counter) the Examiner relied on the very same state-machine passages of Hoogerbrugge ([0013] and [0039]) that the Examiner relied upon for the "counter" of claim 1. That Hoogerbrugge's single state machine was mapped to both the counter and the hysteresis counter confirms that Hoogerbrugge does not disclose two separate counters as now required by amended claim 1. Accordingly, Hoogerbrugge does not disclose each and every element of amended claims 1 and 12, and the § 102(a)(1) rejection is respectfully overcome. Claims 2-4, 6, 9, 11, and 13- 16 and 19 depend from claims 1 and 12 and are allowable for at least the same reasons, and for the additional features each recites.’
Examiner first notes with appreciation Applicant’s comparison of Hoogerbrugge and the instant invention across pages 19-20, including the examples of the bullet points (though also notes, regarding the scenario of the second bullet point, that the result of Hoogerbrugge appears to match the result of the instant invention when the threshold value is two). Nevertheless, Examiner notes that the newly added limitations in claim 1 are contingent limitations. The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met — see MPEP 2111.04. Therefore, Examiner submits that Hoogerbrugge continues to teach claim 1 under a claim mapping wherein the saturating count of Hoogerbrugge corresponds to the claimed counter. In addition, Examiner submits that Hoogerbrugge continues to teach claim 1 (and claims 12 and 20) under the alternative claim mapping wherein the program counter of Hoogerbrugge corresponds to the claimed counter, and the saturating count of Hoogerbrugge corresponds to the claimed hysteresis counter.
Applicant across pages 20-21 argues further claims by referring to arguments made with respect to claims 1 and 12.
Examiner’s response to arguments with respect to claims 1 and 12 is likewise applicable to the arguments directed to the aforementioned further claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KEITH E VICARY/Primary Examiner, Art Unit 2183
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