DETAILED ACTION
This non-final action is responsive to communications: 03/17/2026.
Claims 1- 11 are pending (and subject to examination). Claim 1 is independent.
Election/Restrictions
2. Applicant’s election without traverse of claims 1-11 (Species I) in the reply filed on 03/17/2026 is acknowledged. Claims 12-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 03/17/2026. Claims 1-11 are pending (and subject to examination).
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) MPEP 2163 guidelines teach that drawing and specification must be examined to assess whether an originally-filed claim has adequate support in the written disclosure and/or the drawings. Possession may be shown by a clear depiction of the invention in detailed drawings. C) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. D) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
No Priority
4. See ADS, no priority is in the record.
Information Disclosure Statement
5. Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 04/17/2025. All IDS has been considered.
Specification Objections
6. The Title is objected to because the title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested:
"Memory device with in-memory searching (IMS) cells and method of Euclidean Distance IMS cell encoding"
Applicant is requested to check other claim informality, language issues (e.g., antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
10. Claims 1-2 is/are rejected under 35 U.S.C. 103 as being obvious over TSENG-7155 (US 2023/0197155 A1), in view of TSENG-1496 (US 2023/0061496 A1).
Regarding independent claim 1, TSENG-7155 teaches a memory device (Fig. 1: 10 TCAM device which is nand-type memory. Para [0012]. See Fig. 1-Fig. 11 for illustrated components and functionality. See attached Examiner’s Markup of Figure 5 referenced in rejection), comprising:
a first memory string (Fig. 1: “string” with BL1-SL1) comprising a first switch element (Fig. 2: 202. See Fig. 1 left memory unit in C11) and configured to generate a first cell current signal (Fig. 4 in context of para [0017], para [0023]: generated “current” used for search); and
a second memory string (Fig. 1: “string” with BL2-SL2) comprising a second switch element (Fig. 2: 204. See Fig. 1 right memory unit in C11) and configured to generate a second cell current signal (Fig. 4 in context of para [0017], para [0023]: generated “current” used for search),
wherein the first switch element and the second switch element are configured to operate as a first memory cell storing a first store bit (Fig. 1: C11, Fig. 2: 20 “memory cell”. See para [0014]: “…threshold voltage of the memory units 202 and 204 could be configured to store data representing a first value…a second value…”),
a control terminal of the first switch element and a control terminal of the second switch element are configured to receive a first word line signal and a second word line signal (TSENG-7155 teaches Fig. 2: gate of 202 and gate of 204 receives 212 signal), respectively,
the first word line signal and the second word line signal are configured to carry a first input bit (Table 1-Table3 and Fig. 5: search data VL, VH is carried into 202, 204 when Vsel applied), and
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a summation of a current value (Fig. 7: 402 “current collector” function) of the first cell current signal and a current value of the second cell current signal (Fig. 2, Fig. 5 in context of para [0023], para [0024]: “total current” having level “zero” or level “not zero” which helps to determine match result) is proportional to (proportional to in the relevant context interpreted as a correlation signified by signal on vs. off relationship rather than analog measurement) a square of a difference between a logic value of the first store bit (Fig. 5: stored data VTH, VTL) and a logic value of the first input bit (Fig. 5: search data input VL, VH. Claimed limitation is established from observed results shown in Fig. 5 where it is taught that “total current” having level “zero” correlates (first store bit - first input bit) ^2 ~ 0 value. Also, “total current” having level “not zero” correlates (first store bit - first input bit) ^2 ~ non-zero value. For example, see Fig. 5: Match1 where total current is “zero” from both transistors: Left transistor 202 current is 0 which is proportional to (VH-VTH) ^2 ~ 0 since both logic values are High and cancels each other. Right transistor 204 current is 0 which is proportional to (VL-VTL) ^2 ~ 0 since both logic values are Low and cancels each other. Similarly, Fig. 5: Match2 where total current “0” from both transistors: Left transistor 202 current “0” proportional to (VL-VTL) ^2=0 since both logic values are Low. Right transistor 204 total current “0” proportional to (VH-VTH) ^2=0 since both logic values are High. For Fig. 5: Non 1 (no match) where total current “not zero”/ present from one transistor: Left transistor 202 current “not zero”/ present relates to (VH-VTL) ^2 ~ non-zero value since both logic values are opposite. Right transistor 204 current “0” since transistor channel is turned off. For Fig. 5: Non 1 (no match) where total current “not zero”/ present from one transistor: right transistor 204 current “not zero”/ present relates to (VH-VTL) ^2 ~ non-zero value since both logic values are opposite. Left transistor 202 current “0” since transistor channel is turned off. Thus, the results shown in Fig. 5 in context of Table 1-Table3 disclosure satisfies the claimed limitation).
Even though TSENG-7155 teaches word line signal 212 used with first and second switches, TSENG-7155 is silent with respect to a control terminal of the first switch element and a control terminal of the second switch element are configured to receive a first word line signal and a second word line signal.
TSENG-1496 teaches -
a control terminal of the first switch element (Fig. 8: gate of 402. Also see Fig. 10 for string structure) and a control terminal of the second switch element (Fig. 8: gate of 404. Also see Fig. 10 for string structure) are configured to receive a first word line signal (Fig. 8: B signal) and a second word line signal (Fig. 8: A signal. Fig. 8: 400 is “memory cell” which uses 402, 404. See para [0041], para [0045]).
TSENG-7155 and TSENG-1496 are in the same field of endeavor of CAM search operation using flash memory and they are in analogous field of art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine TSENG-1496’s teachings into the teachings of TSENG-7155 such that independent word line inputs can be employed in the search scheme in order to improve search speed, accelerate response time “…speed up the processing speed of…CAM device…” (para [0054]).
Regarding claim 2, TSENG-7155 and TSENG-1496 teach the memory device of claim 1. TSENG-7155 teaches wherein when the first store bit has a first logic value (Fig. 5: match 1: VTH), the first switch element has a first threshold voltage level (Fig. 5: match 1: VTH),
when the first store bit has a second logic value (Fig. 5: match 2: VTL), the first switch element has a second threshold voltage level (Fig. 5: match 12: VTL),
when the first input bit has the first logic value (Fig. 5: match 1: VH), the first word line signal has a first voltage level (Fig. 5: match 1: Vsel-VH. Transistor VGD biasing coupled to word line signal),
when the first input bit has the second logic value (Fig. 5: match 2: VL), the first word line signal has a second voltage level (Fig. 5: match 2: Vsel-VL. Transistor VGD biasing coupled to word line signal), and
a difference between the first threshold voltage level and the second threshold voltage level (Fig. 5: VTH-VTL. Taken as a quantized difference between logic high and logic low state of a signal) is equal to a difference between the first voltage level and the second voltage level (Fig. 5: VH-VL. Taken as a quantized difference between logic high and logic low state of a signal).
Allowable Subject Matter
Claims 3-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims listed above, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the following limitations of the claims:
Claims 3-8. The memory device of claim 2, wherein when the first store bit has the first logic value, the first switch element has a third threshold voltage level, when the first store bit has the second logic value, the first switch element has a fourth threshold voltage level, when the first input bit has the first logic value, the first word line signal has a third voltage level, when the first input bit has the second logic value, the first word line signal has a fourth voltage level, and a difference between the third threshold voltage level and the fourth threshold voltage level is equal to a difference between the third voltage level and the fourth voltage level.
Claims 9-11. The memory device of claim 2, wherein when each of the first store bit and the first input bit has the first logic value, each of the first cell current signal and the second cell current signal has a first current value, when the first store bit and the first input bit have the first logic value and the second logic value, respectively, the first cell current signal and the second cell current signal have the first current value and a second current value, respectively, and the second current value is larger than the first current value.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
WANG (US 20220284964 A1): all figures and disclosure applicable.
TSENG (US 2023/0036141 A1): Fig. 1-Fig. 10 disclosure applicable for all claims.
LEE (US 2023/0075257 A1): Fig. 1-Fig. 15 disclosure applicable for all claims.
De Santis et al. (US 2018/0322922 A1): De Santis disclosure is applicable for all claims and De Santis teaches an in memory searching device (para [0007]: “two cell NAND CAM”, see Fig. 1-Fig. 10 memory circuit and device), comprising: a plurality of first memory cell strings (see Fig. 6 strings), commonly coupled to a first common bit line (Fig. 6: 610 BL, see also Fig. 3), wherein each of the first memory cell strings (see Fig. 6 strings) comprises a plurality of first data storage layers (Fig. 6: strings comprise data storage layers), the first data storage layers respectively comprise a plurality of first memory cell pairs (Fig. 6 in context of para [0030]: cell pairs 602/604, 606/608 are data storage layers), and the first memory cell pairs are respectively coupled to a plurality of first word line pairs (Fig. 6: word lines shown connected to cells, see Fig. 1, Fig. 2: WL0, WL1); a controller (Fig. 10: 1010 and associated circuitry), coupled to the first memory cell strings (memory array and strings), selecting at least one of the first data storage layers to be at least one selected data storage layer (Fig. 7: 704 in context of para [0030]: e.g., select cell pairs to program data), and providing search data to at least one selected word line pair corresponding to the at least one selected data storage layer (para [0030]: "...Each pair of cells...602/604 and 606/608... are programmed to store the same bit of data...corresponding to a particular bit position of a pattern to be searched...". See also para [0007], para [0010]); and a sensing circuit (Fig. 3, para [0025]: sense circuitry), coupled to the first common bit line and sensing a current on the first common bit line to generate a search result (Fig. 6-Fig. 8 in context of para [0030]: match and no-match condition is determined based on cell pair conducting current or, not conducting current).
Conclusion
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
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