DETAILED ACTION
This non-final action is responsive to the following communications: application filed on 07/01/2024. Applicant’s preliminary amendment filed on 07/01/2024 is being acknowledged and entered: applicant cancelled claims 10, 12, 22, and 24-26 with the amendment.
Claims 1-9, 11, 13-21, and 23 are pending. Claims 1, 15 and 23 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04, Breadth of a claim is not to be equated with indefiniteness, but “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. C) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Per MPEP 2141.02 VI prior art must be considered in its entirety. D) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103 and once a reference teaching product appearing to be substantially identical is made the basis of a rejection, and the examiner presents evidence or reasoning tending to show inherency, the burden of proof shifts to the applicant.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
4. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
5. Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 07/01/2024. This IDS has been considered.
Claim Rejections - 35 USC § 102
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
8. Claims 1, 2, 4-5, 15-16, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shashwat et al. (US 2022/0350357 A1).
Regarding independent claim 1, Shashwat teaches a low dropout (LDO) regulator (Regulator circuitry with active compensation unit for stabilizing voltage output. See e.g., Fig. 1-Fig. 4 circuitry, para [0004]. See Examiner’s Markup of Figure 4) comprising:
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a voltage regulating circuit (Fig. 4: 100d “regulator”) configured to regulate an output voltage (Fig. 4: Vout) of an output node (Fig. 4: 110), the output node being connected with a load (Fig. 4: 106 “load”. See para [0029]),
the output voltage being used as first feedback (Fig. 4: Vout is used as feedback input for the input comparator Fig. 4: 104); and
an adaptive biasing circuit (Fig. 4: 132 compensation stage. Para [0029], para [0031]-para [0032]) configured to
generate a biasing signal (Fig. 4 and para [0037]: Icompn) configured to regulate the output voltage (Fig. 4: Vout) based on a sensing signal (Fig. 4: current at X node) in an internal node (Fig. 4: X node) of the voltage regulating circuit (para [0036]-para [0037]),
the sensing signal (Fig. 4: current at X node) being used as second feedback (Fig. 4, para [0004], para [0037]: Icompn is based on current at X node which is used to control Vout, IL), and
provide the biasing signal (Fig. 4: Icompn) to the voltage regulating circuit (para [0037]: Icompn is added to Isense to adjust Vout and IL. See also para [0035]-para [0037]).
Regarding claim 2, Shashwat teaches the LDO regulator of claim 1, wherein the voltage regulating circuit is configured to regulate the output voltage based on the first feedback being negative feedback (Fig. 4: feedback is provided from circuit system output to input for output stabilization), and
wherein the adaptive biasing circuit is configured to generate the biasing signal based on the second feedback being positive feedback (Fig. 4: feedback is provided from circuit system internal node to output current controlling unit).
Regarding claim 4, Shashwat teaches the LDO regulator of claim 1, wherein the sensing signal comprises a signal related (related by mathematical correlation) to a current that corresponds to a load current flowing from the output node to the load (para [0036]-para [0037]).
Regarding claim 5, Shashwat teaches the LDO regulator of claim 1, wherein the biasing signal (Fig. 4: Icompn) comprises a signal that complements a sink current (Fig. 4: Isense which corresponds to IL), the sink current flowing from the voltage regulating circuit to ground (para [0035]-para [0037]).
Regarding independent claim 15, Shashwat teaches a low dropout (LDO) regulator (Fig. 4: 100d. Regulator circuitry with active compensation unit for stabilizing voltage output. See e.g., Fig. 1-Fig. 4 circuitry, para [0004]. See Examiner’s Markup of Figure 4) comprising:
a first node (Fig. 4: 110) connected with a load (Fig. 4: 106) and configured to provide an output voltage (Fig. 4: Vout);
an LDO current source (Fig. 4: 140) connected between a second node (Fig. 4: X node) and ground (Fig. 4: 111) and configured to drive a sink current (Fig 4 in context of para [0016]: configured to control IL);
a first current mirror (Fig. 4: 134) comprising a first transistor (Fig. 4: 144) and a second transistor (Fig. 4: 142) that are connected with a power voltage terminal (Fig. 4: 108) through a source terminal of each of the first transistor and the second transistor (see Fig. 4: Sa terminal of 144 and Sb terminal of 142 are connected to 108) and with the second node (Fig. 4: X node) through a gate terminal of each of the first transistor and the second transistor (see Fig. 4: 142, 144 gates are connected to X node);
a third transistor (Fig. 4: 102) sharing (commonly connected) the first node (Fig. 4: 110) with a drain terminal of the first transistor (Fig. 4: Da of 144 connected to Vin via channel) through a source terminal of the third transistor (Fig. 4: S1 of 102 is connected to Vin),
the third transistor (Fig. 4: 102) being connected with the second node (Fig. 4: X node is connected to Vin via channel of 142) through a drain terminal of the third transistor (Fig. 4: D1 of 102 is connected to Vin via channel);
a comparator (Fig. 4: 104) configured to output, to a gate terminal of the third transistor (Fig. 4: 102), a result of comparing an output voltage of the first node (Fig. 4: Vout) with a reference voltage (Fig. 4: Vref); and
an adaptive biasing circuit (Fig. 4: 132 compensation stage. Para [0029], para [0031]-para [0032]) configured to generate an additional current (Fig. 4 and para [0037]: Icompn) to complement the sink current (Fig. 4, para [0036], para [0037]: IL which is proportional to Isense) based on a sensing signal (Fig. 4: current at X node) corresponding to a voltage of the second node (Fig. 4: voltage at X node),
the additional current (Fig. 4: Icompn) flowing from the second node (Fig. 4: X node) to ground (Fig. 4: 111).
Regarding claim 16, Shashwat teaches the LDO regulator of claim 15, wherein the additional current is proportional to a magnitude of the sensing signal (para [0036]-para [0037]).
Regarding claim 19, Shashwat teaches the LDO regulator of claim 15, wherein the adaptive biasing circuit is configured to identify whether the sensing signal satisfies a plurality of adaptive biasing conditions (Fig. 4 and para [0037]: Isense being smaller than Icompn), and generate the additional current (Fig. 4: Icompn) based on a result of the identification (para [0035]-para [0037]).
Claim Rejections - 35 USC § 103
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
10. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
11. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
12. Claims 13-14 is/are rejected under 35 U.S.C. 103 as being obvious over Shashwat et al. (US 2022/0350357 A1), in view MOON et al. (US 2021/0225423 A1).
Regarding claim 13, Shashwat teach the LDO regulator of claim 1. Shashwat is silent with respect to driving circuit, parameters and biasing signal details.
MOON teaches the load comprises a driving circuit (Fig. 1: 112) configured to generate output data from input data (para [0031]), and
wherein a value of at least one parameter (Fig. 1: supply voltages) is set based on a plurality of characteristics of the driving circuit (para [0025], para [0030], Fig. 1: TSV. See conductance, size properties of TSV’s), the at least one parameter (Fig. 1: supply voltages) being related to (correlated to) generation of the biasing signal of the adaptive biasing circuit (see Fig. 4: supply voltage of REG is used in the overall feedback mechanism and NT2 voltage control)
Shashwat and MOON are in the same field of endeavor of power supply voltage regulation of integrated circuit and they are in analogous field of art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the circuitry of MOON into the apparatus of Shashwat such that said regulator and driver can be employed in order to reduce noise in introduced in the power supply (MOON para [0006]).
Regarding claim 14, Shashwat and MOON teach the LDO regulator of claim 13. MOON teaches wherein the plurality of characteristics of the driving circuit comprises a plurality of characteristics of a plurality of vias (Fig. 1: TSVs), the plurality of vias being connected with the driving circuit and configured to deliver the output data (Fig. 1: TSV in context of para [0006]).
13. Claim 23 is/are rejected under 35 U.S.C. 103 as being obvious over MOON et al. (US 2021/0225423 A1), in view of Shashwat et al. (US 2022/0350357 A1).
Regarding independent claim 23, MOON teaches a memory device (Fig. 1: 100 “…memory device…of a three-dimensional structure…”, see para [0024] and Fig. 6) comprising:
a buffer die (Fig. 1: 110 buffer die); and
a plurality of core dies (Fig. 1: 120. See also Fig. 6: 120a-c configuration) vertically stacked on the buffer die (Fig. 1: 110, Fig. 6: 110), the plurality of core dies being connected with the buffer die through a plurality of through silicon vias (TSVs) (See Fig. 1: TSV),
wherein the buffer die comprises a first driving circuit (Fig. 1: 112 1st driver circuit) configured to generate first output data from first input data, and output the first output data to a first TSV among the plurality of TSVs (para [0031]: “…may output a data signal received from the interface circuit 113 to the second driver circuit 121 through one or more corresponding TSVs…”); and
a first low dropout (LDO) regulator (Fig. 1: 111) configured to provide, as a first supply voltage, a first output voltage of a first output node to the first driving circuit (para [0025]: VDD, VDDQL, VSS).
Shashwat teaches -
first LDO regulator (Fig. 4: 100d) comprises a first voltage regulating circuit (Fig. 4: 100d) configured to regulate the first output voltage (Fig. 4: Vout) of the first output node (Fig. 4: 110) based on the first output voltage (Fig. 4: based on Vout feedback to 104 input); and
a first adaptive biasing circuit (Fig. 4: 132) configured to generate a first biasing signal (Fig. 4: Icompn) configured to regulate the first output voltage (Fig. 4: Vout) based on a first sensing signal (Fig. 4: current at X node) in a first internal node (Fig. 4: X node) of the first voltage regulating circuit (Fig. 4: 100d).
MOON and Shashwat are in the same field of endeavor of power supply voltage regulation of integrated circuit and they are in analogous field of art. An ordinary skill in the art would understand the use of Shashwat’s circuitry into the apparatus of MOON.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the circuitry of Shashwat into the apparatus of MOON such that regulator with stable output and smaller area can be employed in order to have stable system capable of handling wide range of load currents (Shashwat Abstract, para [0004]])
Prior Art Not Relied Upon but Pertinent
9. The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
JOO (US 2021/0397207 A1): Fig. 1-Fig. 18 disclosure applicable for all claims.
Kadanda (US 11,416,014 B2): Fig. 1-Fig. 7 disclosure applicable for all claims.
Agarwal (US 2015/0234404 A1): Fig. 1-Fig. 3 disclosure applicable for all claims.
Cazzaniga (US 2010/0074034 A1): Fig. 1-Fig. 5 disclosure applicable for all claims. Cazzaniga teaches a voltage generator (Fig. 1: 100 “voltage regulator” and associated circuitry. See also Fig. 4 and Fig. 5) comprising: at least one driving circuit (Fig. 1: 102. See Fig. 5: 102) connected to a plurality of word lines of a memory device (e.g. terminal B of Fig. 5: 200 “memory cell”. para [0041]: “word lines” in a cross-point nonvolatile memory array), the at least one driving circuit (Fig. 5: 102) configured to provide a current (Fig. 5: I_Load) for increasing voltages of the plurality of word lines (Fig. 5: Vout) based on a reference voltage (Fig. 5 in context of para [0052]: input reference voltage VBG which coupled with feedback voltage from output Vout); a current sensing circuit (means for detecting e.g. Fig. 7D: ILoad) configured to detect a magnitude of a charge current input (e.g. Fig. 7D: ILoad) to the at least one driving circuit, a peak detect circuit (means for detecting e.g. Fig. 7D: Imax or Fig. 9: ILoadmax) configured to compare the detected magnitude of the charge current with a peak current value (Fig. 7D: ILoad vs. Imax is detected and taken as circuitry functionality)
It is suggested that applicant consider all prior arts made of record.
Allowable Subject Matter
Claims 3, 6-9, 11, and 17-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims listed, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the following limitations of the claims.
Claim 3: The LDO regulator of claim 2, wherein the adaptive biasing circuit is configured to limit the positive feedback on the output voltage to be less than the negative feedback on the output voltage.
Claims 6-9, 11: The LDO regulator of claim 5, wherein the voltage regulating circuit comprises: a flipped voltage follower comprising a plurality of transistors; and a comparator configured to output, to the flipped voltage follower, a result of comparing the first feedback with a reference voltage.
Claim 17. The LDO regulator of claim 15, wherein a current, flowing from the first node to the second node in a channel of the third transistor, is maintained within a threshold range in a recovery period according to the output voltage being dropped due to the load.
Claim 18. The LDO regulator of claim 15, wherein the adaptive biasing circuit is configured to downscale the sensing signal, and generate the additional current based on the sensing signal that has been downscaled.
Claim 20. The LDO regulator of claim 19, wherein the plurality of adaptive biasing conditions correspond to a plurality of conditions under which the sensing signal corresponds to a low-frequency band.
Claim 21. The LDO regulator of claim 15, wherein the adaptive biasing circuit comprises: a second current mirror comprising a fourth transistor connected with the power voltage terminal through a source terminal of the fourth transistor, connected with the second node through a gate terminal of the fourth transistor, and connected with a fourth node through a drain terminal of the fourth transistor; a fifth transistor connected with the fourth node through a gate terminal of the fifth transistor; and a sixth transistor connected with the fourth node through a gate terminal of the sixth transistor, wherein the sixth transistor is configured to copy a current to generate the additional current, the current flowing from the fourth node in a channel of the fifth transistor to ground.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached on 7:00 am-4:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander George Sofocleous can be reached on (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUSHFIQUE SIDDIQUE/
Primary Examiner, Art Unit 2825