DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The IDS filed on 07/01/2024, 11/19/2025, and 09/14/2026 have been considered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 10-12, 14, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Smith (U.S. Pub. 2023/0378138) in view of Xie et al. (U.S. Pub. 2024/0145311).
In re claim 1, Smith discloses a semiconductor device, comprising: a bottom field effect transistor (FET) 110 having a bottom source/drain (S/D) structure 113 (see paragraphs [0143], [0155] and figs. 1A-B); a top FET 120 above the bottom FET 110, having a top S/D structure 123 (see paragraphs [0143], [0155] and figs. 1A-B); a backside top contact 131e that is in electrical contact with a side surface of the top S/D structure 123 and that extends below the bottom FET 110 (see paragraph [0147] and figs. 1A-B); and a dielectric liner, disposed along sidewalls of the backside top contact 131e, that separates the backside top contact 131e from the bottom S/D structure 113 (see paragraph [0147] and figs. 1A-B).
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Smith is silent to wherein the backside top contact that is in electrical contact with a bottom surface of the top S/D structure.
However, Xie discloses in a same field of endeavor, a semiconductor device, including, inter-alia, a backside top contact 102 that is in electrical contact with a bottom surface 138 and a side surface 140 of the top S/D structure 136 (see paragraph [0037] and fig. 1).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Xie into the semiconductor device of Smith in order to enable wherein the backside top contact that is in electrical contact with a bottom surface of the top S/D structure in Smith to be formed in order to reduce resistance between the backside top contact and the top S/D structure and enhance the performance of the semiconductor device. Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id.
In re claim 2, as applied to claim 1 above, Smith in combination with Xie is silent to wherein the top S/D structure is laterally shifted relative to the bottom S/D structure. However, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art to re-configurate the arrangement of the top S/D structure and the bottom S/D structure so that the top S/D structure is laterally shifted relative to the bottom S/D structure in order to improve the performance of the semiconductor device.
In re claim 3, as applied to claim 1 above, Smith in combination with Xie wherein the semiconductor device further comprising a backside power plane 141 below the bottom FET 110 (see paragraph [0143] and figs. 1A-B of Smith).
In re claim 4, as applied to claim 3 above, Smith discloses wherein the backside top contact 131e extends to the backside power plane 141 (see paragraphs [0143], [0147] and figs. 1A-B) but is silent to wherein the backside top contact extends through the backside power plane, wherein the dielectric liner further separates the backside top contact from the backside power plane.
However, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art to form the backside top contact to extend through the backside power plane and wherein a dielectric liner separates the backside top contact from the backside power plane in order to improve the performance of the semiconductor device.
In re claim 5, as applied to claim 3 above, Smith in combination with Xie discloses wherein the semiconductor device further comprising a backside bottom contact that is in electrical contact with the backside power plane 141 and the bottom S/D structure 113 (see paragraphs [0145], [0147] and figs. 1A-B of Smith).
In re claim 6, as applied to claim 5 above, Smith in combination with Xie discloses wherein the dielectric liner is in direct contact with the backside bottom contact (see paragraphs [0145], [0147] and figs. 1A-B of Smith).
In re claim 7, as applied to claim 1 above, Smith in combination with Xie discloses wherein the semiconductor device further comprising a gate cut structure isolating the backside top contact 131e from a neighboring top FET (see paragraph [0161] and figs. 1A-B of Smith).
In re claim 10, as applied to claim 1 above, Smith in combination with Xie discloses wherein the side surface of the top S/D structure 123 is a flat, vertical surface (see paragraph [0147] and figs. 1A-B of Smith).
In re claim 11, Smith discloses a semiconductor device, comprising: a first bottom field effect transistor (FET) 110 having a first bottom source/drain (S/D) structure 113 (see paragraphs [0145], [0147] and figs. 1A-B); a first top FET 120 above the first bottom FET 110, having a first top S/D structure 123 that is above the first bottom S/D structure 113 (see paragraphs [0145], [0147] and figs. 1A-B); a backside power plane 141 below the first bottom FET 110 (see paragraph [0147] and figs. 1A-B); a backside bottom contact that is in electrical contact with the backside power plane 141 and the first bottom S/D structure 113; a backside top contact 131e that extends to the backside power plane 141 from below the first bottom FET 110 and that is in electrical contact with a side surface of the first top S/D structure 123 (see paragraphs [0147] and figs. 1A-B).
Smith is silent to a first top S/D structure that is laterally shifted relative to the first bottom S/D structure; a backside top contact that extends through the backside power plane from below the first bottom FET and that is in electrical contact with a bottom surface of the first top S/D structure; and a dielectric liner, disposed along sidewalls of the backside top contact, that separates the backside top contact from the backside power plane.
However, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art to re-configurate the arrangement of the first top S/D structure and the first bottom S/D structure so that the first top S/D structure is laterally shifted relative to the first bottom S/D structure and to form the backside top contact to extend through the backside power plane and wherein a dielectric liner disposed along sidewalls of the backside top contact to separates the backside top contact from the backside power plane in order to improve the performance of the semiconductor device.
Smith is further silent to wherein the backside top contact that is in electrical contact with a bottom surface of the first top S/D structure.
However, Xie discloses in a same field of endeavor, a semiconductor device, including, inter-alia, a backside top contact 102 that is in electrical contact with a bottom surface 138 and a side surface 140 of the first top S/D structure 136 (see paragraph [0037] and fig. 1).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Xie into the semiconductor device of Smith in order to enable wherein the backside top contact that is in electrical contact with a bottom surface of the first top S/D structure in Smith to be formed in order to reduce resistance between the backside top contact and the top S/D structure and enhance the performance of the semiconductor device. Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id.
In re claim 12, as applied to claim 11 above, Smith in combination with Xie discloses wherein the semiconductor device further comprising a second top FET adjacent to the first top FET 120, with a gate cut structure isolating the backside top contact 131e from a second top S/D structure of the second top FET (see paragraph [0147] and figs. 1A-B of Xie).
In re claim 14, as applied to claim 12 above, Smith and Xie discloses wherein the semiconductor device further comprising a second bottom FET adjacent to the first bottom FET (see paragraph [0147] and figs. 1A-B) but is silent to wherein a second bottom S/D structure that is laterally shifted relative to the second top S/D structure.
However, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art to re-configurate the arrangement of the second top S/D structure and the second bottom S/D structure so that the second bottom S/D structure is laterally shifted relative to the second top S/D structure in order to improve the performance of the semiconductor device.
In re claim 15, as applied to claim 14 above, Smith in combination with Xie discloses wherein the semiconductor device further comprising a frontside top contact that makes an electrical connection to the second top S/D structure from above the first top FET 120 and a frontside bottom contact that makes an electrical connection to the second bottom S/D structure from above the first top FET 120 (see paragraph [0143] and figs. 1A-B of Smith).
Claim(s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Smith (U.S. Pub. 2023/0378138) in view of Xie et al. (U.S. Pub. 2024/0145311) and Yang et al. (U.S. Pub. 2020/0266286).
In re claim 16, Smith discloses a semiconductor device, comprising: a first bottom field effect transistor (FET) 110 having a first bottom source/drain (S/D) structure 113 (see paragraphs [0143], [0147] and figs. 1A-B); a first top FET 120 above the first bottom FET 110, having a first top S/D structure 123; a second top FET adjacent to the first top FET; a second bottom FET adjacent to the first bottom FET (see paragraphs [0143], [0147] and figs. 1A-B); a backside top contact 131e that is in electrical contact with a side surface of the first top S/D structure123 and that extends below the first bottom FET 110; a dielectric liner, disposed along sidewalls of the backside top contact 1312, that separates the backside top contact from the first bottom S/D structure 113 (see paragraph [0147] and figs. 1A-B); and a gate cut structure that isolates the backside top contact 131e from the second top FET (see paragraph [0147] and figs. 1A-B).
Smith is silent to wherein a backside top contact that is in electrical contact with a bottom surface of the first top S/D structure and a gate cut structure that includes a dielectric liner of a first dielectric material and a dielectric fill of a second dielectric material.
However, Xie discloses in a same field of endeavor, a semiconductor device, including, inter-alia, a backside top contact 102 that is in electrical contact with a bottom surface 138 and a side surface 140 of the top S/D structure 136 (see paragraph [0037] and fig. 1).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Xie into the semiconductor device of Smith in order to enable wherein the backside top contact that is in electrical contact with a bottom surface of the top S/D structure in Smith to be formed in order to reduce resistance between the backside top contact and the top S/D structure and enhance the performance of the semiconductor device. Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id.
Smith and Xie are silent to wherein a gate cut structure that includes a dielectric liner of a first dielectric material and a dielectric fill of a second dielectric material.
However, Yang discloses in a same field of endeavor, a semiconductor device including, inter-alia, wherein a gate cut structure 100 that includes a dielectric liner 154 of a first dielectric material and a dielectric fill 158 of a second dielectric material (see paragraph [0032] and fig. 6).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Yang into the semiconductor device of Smith in order to enable wherein a gate cut structure that includes a dielectric liner of a first dielectric material and a dielectric fill of a second dielectric material in Smith to be formed in order to improve the performance of the semiconductor device (see paragraph [0033] of Yang).
In re claim 17, as applied to claim 16 above, Smith in combination with Xie and Yang discloses wherein the semiconductor device further comprising a backside power plane 141 below the first bottom FET 110 (see paragraph [0143] and figs. 1A-B of Smith).
In re claim 18, as applied to claim 17 above, Smith in combination with Xie and Yang is silent to wherein the backside top contact penetrates the backside power plane, with the dielectric liner insulating the backside top contact from the backside power plane.
However, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art to form the backside top contact to penetrate through the backside power plane with a dielectric liner insulating the backside top contact from the backside power plane in order to improve the performance of the semiconductor device.
In re claim 19, as applied to claim 17 above, Smith in combination with Xie and Yang discloses wherein the semiconductor device further comprising a backside bottom contact that is in electrical contact with the backside power plane 141 and the first bottom S/D structure 113 (see paragraph [0143] and figs. 1A-B of Smith).
In re claim 20, as applied to claim 19 above, Smith in combination with Xie and Yang discloses wherein the dielectric liner is in direct contact with the backside bottom contact 131e (see paragraphs [0145], [0147] and figs. 1A-B of Smith).
Claim(s) 8, 9, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Smith (U.S. Pub. 2023/0378138) in view of Xie et al. (U.S. Pub. 2024/0145311), as applied to claims 7 and 12 above, and further in view of Yang et al. (U.S. Pub. 2020/0266286).
In re claims 8, 9, and 13, as applied to claims 7 and 12 above, respectively, Smith and Xie are silent to wherein the gate cut structure includes a dielectric liner of a first dielectric material and a dielectric fill of a second dielectric material, and wherein the first dielectric material is silicon nitride and the second dielectric material is silicon dioxide.
However, Yang discloses in a same field of endeavor, a semiconductor device including, inter-alia, wherein a gate cut structure 100 that includes a dielectric liner 154 of a first dielectric material and a dielectric fill 158 of a second dielectric material, wherein the first dielectric material 154 is silicon nitride and the second dielectric material 158 is silicon dioxide (see paragraph [0032] and fig. 6).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Yang into the semiconductor device of Smith in order to enable wherein the gate cut structure includes a dielectric liner of a first dielectric material and a dielectric fill of a second dielectric material, and wherein the first dielectric material is silicon nitride and the second dielectric material is silicon dioxide in Smith to be formed in order to improve the performance of the semiconductor device (see paragraph [0033] of Yang).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Engel et al. (U.S. Pub. 2023/0369222) discloses a semiconductor device, including, inter-alia, a backside access structure 224 can be associated with some of the source or drain structures 214 (see paragraph [0034] and fig. 2A).
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/KHIEM D NGUYEN/Primary Examiner, Art Unit 2892
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