DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 4-6 have been considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, and 4-6 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The specification as filed with respect to the elected embodiment of fig. 15 fails to provide support for the claim limitation “one of the plurality of gate electrodes separate the carrier injection suppression layer from the insulated gate bipolar transistor region” as recited at the last two lines of the claim.
As explained in the specification, element 4b is disclosed as the dummy gate electrode and element 4a is described as the gate electrode. These gate-type structures have different functions, the dummy gate 4b is connected to first electrode 6 while the gate electrode 4a is connected to the gate signal. Therefore, when looking at fig. 15, the claim limitation requiring the carrier injection suppression layer 82 being separated from the IGBT region 10 by one of the plurality of gate electrodes is not supported since fig. 15 shows element 4b separating 82 and the IGBT region 10.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, and 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Murakawa et al. (US PGPub 2019/0252534; hereinafter “Murakawa”) in view of Soneda (US PGPub 2016/0148928) as evidenced by Soeno (US PGPub 2012/0080718).
Re claim 1: Murakawa teaches (e.g. figs. 6, 3A, 3B) a semiconductor device comprising: a semiconductor substrate (10) including a drift layer (n--type drift layer 11; e.g. paragraph 28) of a first conductivity type (n-type) between a first main surface (top surface of 10; hereinafter “1MS”) and a second main surface (bottom surface of 10; hereinafter “2MS”) facing the first main surface (1MS); a hole injection region (IGBT region 1a; e.g. paragraph 46) including: a hole injection layer (15a formed in p-type base layer 12a; e.g. paragraph 37) of a second conductivity type (p-type) provided in a surface layer (12a) on the first main surface (1MS) side of the semiconductor substrate (10), and a semiconductor layer (p-type collector 21; e.g. paragraph 48) of the second conductivity type (p-type) provided in the surface layer (10b) on the second main surface side (2MS); a diode region (diode region 1b; e.g. paragraph 46) including: an anode layer (p-type base layer 12b; e.g. paragraph 39) of the second conductivity type (p-type) provided in the surface layer (upper surface of 10) on the first main surface (1MS) side of the semiconductor substrate (10), an anode contact layer (contact region 15b; e.g. paragraph 37) of the second conductivity type (p-type) selectively provided in the surface layer (upper surface of 10) on the first main surface (1MS) side of the anode layer (12b), the anode contact layer (15b) having a higher impurity concentration (15b is p and 12b is p-) than the anode layer (12b), and a cathode layer (n-type cathode 22; e.g. paragraph 48) of the first conductivity type (n-type) provided in the surface layer (bottom surface of 10) on the second main surface (2MS) side of the semiconductor substrate (10), the diode region (1b) having no semiconductor layer (1b lack any n-type regions within 12b) of the first conductivity type (n-type) between the second main surface (2MS) side of the anode layer (12b) and the first main surface (1MS); a boundary region (boundary region 1c; e.g. paragraph 46) including: a boundary portion semiconductor layer (12b within 1c) of the second conductivity type (p-type) provided between the diode region (1b) and the hole injection region (1a), the boundary portion semiconductor layer (12b within 1c) provided in the surface layer (upper surface of 10) on the first main surface (1MS) side of the semiconductor substrate (10), a boundary portion contact layer (p-type contact region 15c) of the second conductivity type (p-type) provided in the surface layer (upper surface of 10) of the boundary portion semiconductor layer (12b within 1c), the boundary portion contact layer (15c) having a higher impurity concentration (15c is p and 12b within 1c is p-) than the boundary portion semiconductor layer (12b within 1c), and the semiconductor layer (21) of the second conductivity type (p-type) provided to protrude from the hole injection region (1a) in the surface layer (bottom surface of 10) on the second main surface (2MS) side of the semiconductor substrate (10); and a dummy gate electrode (17 within 1c; hereinafter “DGE”) provided on the first main surface (1MS) side of the semiconductor substrate (10) between the diode region (1b) and the boundary region (1c), the dummy gate electrode (DGE) facing the boundary portion semiconductor layer (12b within 1c) and the drift layer (11) via a gate insulating film (gate insulating film 16; e.g. paragraph 41), the dummy gate electrode (DGE) to which no gate driving voltage is applied (DGE is provided with emitter voltage as can be seen in fig. 6), wherein the hole injection region (1a) includes the hole injection layer (12a within 1a) of the second conductivity type (p-type) as a base layer (first base layer 12a; e.g. paragraph 30) of the second conductivity type (p-type), and the semiconductor layer (21) of the second conductivity type (p-type) as a collector layer (collector 21; e.g. paragraph 48) of the second conductivity type (p-type), and the hole injection region (1a) is an insulated gate bipolar transistor region (IGBT region 1a; e.g. paragraph 25) including: an emitter layer (N+ emitter 14; e.g. paragraph 31) of the first conductivity type (n-type) selectively provided in the surface layer (upper surface of 10) on the first main surface (1MS) side of the base layer (12a), a gate electrode (17 within 1a; hereinafter “GE”) provided on the first main surface (1MS) side of the semiconductor substrate (10), a plurality of the gate electrodes (GE) arranged side by side in a direction along the first main surface (1MS), the gate electrode (GE) facing the emitter layer (14), the base layer (12a), and the drift layer (11) via the gate insulating film (16).
Murakawa is silent as to explicitly teaching a carrier injection suppression layer of the first conductivity type provided in a surface layer of the boundary portion semiconductor layer, and the insulated gate bipolar transistor region further includes a base contact layer provided in the surface layer on the first main surface side of the base layer, in a direction in which a plurality of the gate electrodes are arranged side by side, the carrier injection suppression layer is adjacent to the base contact layer via one of the plurality of gate electrodes; and the hole injection region and the diode region are not directly arranged adjacent to each other, and the one of the plurality of gate electrodes separate the carrier injection suppression layer from the insulated gate bipolar transistor region.
Soneda teaches at paragraph 20 the structure of fig. 1 prevents holes from being injected from the P-base 32 from the IGBT region 12 to the FWD region 14 and further teaches (e.g. fig. 1) a carrier injection suppression layer (n+ region 30a provided to overlap P+ collector 36) of the first conductivity type (p-type) provided in a surface layer (upper surface of device of fig. 1) of the boundary portion semiconductor layer (12b within 1c of Murakawa), and the insulated gate bipolar transistor region (transistor 12; e.g. paragraph 18) further includes a base contact layer (p+ region 30b; e.g. paragraph 20) provided in the surface layer (upper surface of device of fig. 1) on the first main surface (upper surface of device of fig. 1) side of the base layer (32), in a direction in which a plurality of the gate electrodes (22 within 12) are arranged side by side, the carrier injection suppression layer (30a) is adjacent to the base contact layer (30b) via one of the plurality of gate electrodes (22 within 12).
The combined teachings of Murakawa and Soneda teaches the hole injection region (1a of Murakawa) and the diode region (1b of Murakawa) are not directly arranged adjacent to each other (1c of Murakawa is arranged between 1a and 1b), and the one of the plurality of gate electrodes (17 of Murakawa connected to G) separate the carrier injection suppression layer (30a of Soneda within 1c of Murakawa) from the insulated gate bipolar transistor region (1a of Murakawa).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the n-type region provided in the boundary region as taught by Soneda in the device of Murakawa in order to have the predictable result of preventing the accumulation of hole in the drift region of the boundary region so that holes can be restored to the IGBT region and the resistance of the drift region does not increase the on-voltage is reduced (see paragraphs 4, 6, and 29 of Soeno).
Re claim 4: Murakawa teaches the semiconductor device according to claim 1, wherein, in the boundary region (1c), a plurality of first dummy gate electrodes (two left DGE) are arranged side by side in a direction along the first main surface (upper surface of 10) on the first main surface (1MS) side of the semiconductor substrate (10), in the diode region (1b), a plurality of second dummy gate electrodes (two right DGE) are provided on the first main surface (1MS) side of the semiconductor substrate (10) and arranged side by side in the direction along the first main surface (1MS), each of the plurality of second dummy gate electrodes (two right DGE) faces the anode layer (12b of 1b) and the drift layer (11) via the gate insulating film (16), and is not applied with the gate driving voltage (DGE has emitter voltage applied), the dummy gate electrode (DGE) includes the plurality of first dummy gate electrodes (two left DGE) and the plurality of second dummy gate electrodes (two right DGE) and a ratio of an area where the anode contact layer (15b) is arranged between second dummy gate electrodes (two right DGE) adjacent to each other among the plurality of second dummy gate electrodes (two right DGE) is higher than a ratio of an area where the boundary portion contact layer (15c) is arranged between first dummy gate electrodes (two right DGE) adjacent to each other among the plurality of first dummy gate electrodes (two right DGE).
Re claim 5: Murakawa teaches the semiconductor device according to claim 1, wherein the diode region (1b) further includes a cathode portion second conductivity type semiconductor layer (12b within 1b) of the second conductivity type (p-type) provided to be sandwiched between the cathode layers (22) in the surface layer on the second main surface (2MS) side of the semiconductor substrate (10).
Re claim 6: Murakawa teaches the semiconductor device according to claim 5, wherein an impurity concentration distribution of the second conductivity type (p-type) in a depth direction from the second main surface (2MS) toward the first main surface (1MS) is a same in the collector layer (21) and the cathode portion second conductivity type semiconductor layer (12b within 1b).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
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