DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
IDS
The IDS document(s) filed on 07/01/2024, 03/13/2025 and 05/08/2025 have been considered. Copies of the PTO-1449 documents are herewith enclosed with this office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5, 7 and 9-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Goto et al. (US 2022/0320340 A1), hereafter “Goto”.
As to claim 1, Goto teaches a semiconductor device comprising:
a first insulating layer (103a, Fig. 1C, ⁋ [0153]);
an oxide semiconductor layer (108, Fig. 4B, ⁋ [0112]) having a polycrystalline structure (⁋ [0113]) on the first insulating layer;
a gate insulating layer (110, ⁋ [0084]) on the oxide semiconductor layer;
a gate wiring (112, ⁋ [0084]) on the gate insulating layer; and
a second insulating layer (118, ⁋ [0140] on the gate wiring, wherein
the oxide semiconductor layer has a first region (108C, ⁋⁋ [0085] – [0086]), a second region (108L1 to 108Lp) and a third region (108N) aligned toward a first direction,
the first region overlaps (108C) the gate insulating layer (110) and the gate wiring (112) (Fig. 4B),
the third region (108L1 to 108Lp) is in contact with the second insulating layer (118) (Fig. 4B), and
a distance (D1, see annotated Fig. 4B below) from a top surface of the second region to a top surface of the second insulating layer is longer than a distance (D2, see annotated Fig. 4B below) from a top surface of the third region to the top surface of the second insulating layer.
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As to claim 2, Goto teaches the semiconductor device according to claim 1, wherein the second region (108L1 to 108Lp) is in contact with the gate insulating layer (110) and does not overlap the gate wiring (112) (Fig. 4B).
As to claim 3, Goto teaches the semiconductor device according to claim 1, wherein a top surface of the second insulating layer (118) on the second region (108L1 to 108Lp) is inclined with respect to the top surface of the second region (Fig. 4B shows the top surface of 118 to have an incline).
As to claim 5, Goto teaches the semiconductor device according to claim 1, wherein a top surface (110s) of the gate insulating layer (110) on the second region (108L1 to 108Lp) is inclined with respect to the top surface of the second region (⁋ [0215], “a side surface 110S of the insulating layer 110 may have a slope shape”).
As to claim 7, Goto teaches the semiconductor device according to claim 1, wherein a top surface of the second insulating layer (118) within a predetermined distance (length of second region 108L1 to 108Lp) from an edge of the portion of the gate wiring (112) not overlapping the oxide semiconductor layer is inclined with respect to a top surface of the gate wiring (Fig. 4B shows top surface of 118 is inclined with respect to top surface of 112 within 108L1 to 108Lp).
As to claim 9, Goto teaches the semiconductor device according to claim 1, wherein the second insulating layer (118) includes a silicon oxide layer (⁋ [0140]).
As to claim 10, Goto teaches the semiconductor device according to claim 1, wherein the first region (108C) is a channel region (⁋ [0085]), and the second region is a region of lower resistance than the channel region (⁋ [0086]).
As to claim 11, Goto teaches the semiconductor device according to claim 10, wherein the third region (108N) is a region of lower resistance than the second region (⁋ [0086]).
As to claim 12, Goto teaches the semiconductor device according to claim 1, further comprising a metal oxide layer (103c, Fig. 1C, ⁋ [0160]) between the first insulating layer (103a) and the oxide semiconductor layer (108).
As to claim 13, Goto teaches the semiconductor device according to claim 12, wherein the metal oxide layer (103c) and the oxide semiconductor layer (108) have the same pattern shape (Fig. 1C+4B shows both having the same pattern shape).
As to claim 14, Goto teaches the semiconductor device according to claim 1, wherein the oxide semiconductor layer (108) contains at least two or more metallic elements including indium (⁋ [0118]), and a ratio of indium to the at least two or more metallic elements is 50% or more (⁋ [0118], “In:M:Zn=3:1:2”).
As to claim 15, Goto teaches a display device (700, Fig. 22A, ⁋ [0459]) having a plurality of pixels (702), each of the plurality of pixels comprising the semiconductor device according to claim 1 (⁋ [0462]).
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4, 6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Goto.
As to claim 4, Goto teaches the semiconductor device according to claim 3, but fails to teach wherein the inclination angle of the top surface of the second insulating layer with respect to the top surface of the second region is more than 5 degrees and less than 20 degrees.
Goto does teach an inclination angle of the top surface of the second insulating layer with respect to the top surface of the second region, but fails to teach the inclination angle within the claimed range.
Examiner notes the Applicant has not specified a criticality to the dimensions.
If the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device: In re Gardner v. TEC Systems, Inc., 220 USPQ 777.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the device of Goto and obtain the claimed range of the inclination angle because selecting and adjusting relative dimensions to achieve the claimed arrangement would have been a matter within the ordinary skill of the artisan and would have not have required undue experimentation or yielded an unexpected result.
As to claim 6, Goto teaches the semiconductor device according to claim 1, wherein a length of the second region in the first direction is more than 0.3 µm and less than 1.0 µm (⁋ [0228]). Examiner notes that Goto teaches the smallest the range can be with a minimum of 2 regions (108L1+108L2) is 0.1 μm (“each range preferably from 50 nm to 1 μm”) and Goto further explains device complications if the length is greater than 2 μm (“the source-drain resistance increases and the driving speed of the transistor may be low”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teaching of second region length taught by Goto, because where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990) (The prior art taught carbon monoxide concentrations of "about 1-5%" while the claim was limited to "more than 5%." The court held that "about 1-5%" allowed for concentrations slightly above 5% thus the ranges overlapped.); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997) (Claim reciting thickness of a protective layer as falling within a range of "50 to 100 Angstroms" considered prima facie obvious in view of prior art reference teaching that "for suitable protection, the thickness of the protective layer should be not less than about 10 nm [i.e., 100 Angstroms]." The court stated that "by stating that ‘suitable protection’ is provided if the protective layer is ‘about’ 100 Angstroms thick, [the prior art reference] directly teaches the use of a thickness within [applicant’s] claimed range.") (See MPEP 2144.05).
As to claim 8, Goto teaches the semiconductor device according to claim 7, wherein the predetermined distance is more than 0.3 µm and less than 1.0 µm. Goto teaches (⁋ [0228]), in regards to the length of the second region, i.e. predetermined distance, the smallest the range can be with a minimum of 2 regions (108L1+108L2) is 0.1 μm (“each range preferably from 50 nm to 1 μm”) and Goto further explains device complications if the length is greater than 2 μm (“the source-drain resistance increases and the driving speed of the transistor may be low”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teaching of the second region length taught by Goto, because where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990) (The prior art taught carbon monoxide concentrations of "about 1-5%" while the claim was limited to "more than 5%." The court held that "about 1-5%" allowed for concentrations slightly above 5% thus the ranges overlapped.); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997) (Claim reciting thickness of a protective layer as falling within a range of "50 to 100 Angstroms" considered prima facie obvious in view of prior art reference teaching that "for suitable protection, the thickness of the protective layer should be not less than about 10 nm [i.e., 100 Angstroms]." The court stated that "by stating that ‘suitable protection’ is provided if the protective layer is ‘about’ 100 Angstroms thick, [the prior art reference] directly teaches the use of a thickness within [applicant’s] claimed range.") (See MPEP 2144.05).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARNELL HUNTER whose telephone number is (571)270-1796. The examiner can normally be reached Monday - Friday 7:30 am - 4:30pm.
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/CARNELL HUNTER III/Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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