DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
2. Claim 1 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Choi et al. U.S. Patent Application Publication 2024/0074236 A1 (the ‘236 reference).
The reference discloses in Fig. 4 and related text a display device as claimed.
Referring to claim 1, the reference discloses a display device comprising:
a first electrode (a terminal portion of semiconductor layer 800 (~800), para [71] (paragraph(s) [0071])) disposed on a first conductive layer (800) on a substrate (1000);
a first insulating layer (1110, para [72]) disposed on the substrate (1000), the first insulating layer (1110) covering the first conductive layer (800);
a second electrode (a terminal portion of light-blocking layer 400 (~400), para [88]) disposed on a second conductive layer (400) on the first insulating layer (1110);
a second insulating layer (1150, para [81]) disposed on the first insulating layer (1110), the second insulating layer (1150) covering the second conductive layer (400);
an active layer (an active portion of semiconductor layer 410 (~410), para [70]) of a transistor (driving transistor DT DR Tr (para [56, 70])) disposed on a semiconductor layer (410) on the second insulating layer (1150);
a gate insulating layer (a portion of 1160 (~1160), para [96]) disposed on the second insulating layer (1150), the gate insulating layer (~1160) disposed on a part of the active layer (~410);
a third electrode (gate electrode 420, para [70]) disposed on a third conductive layer (a gate line comprising gate electrode 420; see Fig. 2 which depicts respective gate lines GL, SL, and gate line including node N1 comprising respective gate electrodes) on the gate insulating layer (~1160);
a third insulating layer (1170, para [97]) disposed on the second insulating layer (1150), the third insulating layer (1170) covering the semiconductor layer (410), the gate insulating layer (~1160), and the third conductive layer (the gate line comprising the third (gate) electrode 420); and
a fourth electrode (820S, para [99]) disposed on a fourth conductive layer (comprising 820S, 820D, 721S,…) on the third insulating layer (1170),
wherein the fourth electrode (820S) overlaps the first electrode (~800), and is directly electrically connected to the first electrode through a first contact hole (not labeled) penetrating the first insulating layer (1110, the second insulating layer (1150), and the third insulating layer (1170).
Allowable Subject Matter
3. Claims 12-20 are allowable over the prior art of record.
Claims 2-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to teach or render obvious a display device and a method for manufacturing a display device with all exclusive limitations as recited in claims 2, 6, 12 and 17, which may be characterized (claim 2) in that the fourth electrode is directly electrically connected to the third electrode through a second contact hole penetrating the third insulating layer, and in that the first electrode, the third electrode, and the fourth electrode constitute a first capacitor electrode of a capacitor, (claim 6) the transistor further comprises a gate electrode disposed on the third conductive layer and disposed on a part of the active layer, (claim 12) in that a capacitor comprises a first electrode disposed on a first conductive layer on a substrate, a second electrode disposed on a second conductive layer on the first conductive layer, a third electrode disposed on a third conductive layer on the second conductive layer and a fourth electrode disposed on a fourth conductive layer on the third conductive layer, and in that the fourth electrode is directly electrically connected to the first electrode through a first contact hole penetrating the first insulating layer, the second insulating layer, and the third insulating layer, and directly electrically connected to the third electrode through a second contact hole penetrating the third insulating layer, and (claim 17) in etching the conductive film and the gate insulating layer to form a first gate insulating layer and a gate electrode on a part of the active layer, and form a second gate insulating layer and a third electrode on a part of the second insulating layer.
Conclusion
4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TU TU V HO whose telephone number is (571)272-1778. The examiner can normally be reached on Monday to Thursday 6:30 - 15:00, Monday through Thursday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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07-29-2026
/TU-TU V HO/Primary Examiner, Art Unit 2818
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