DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Specifically, the sixth indented limitation of claim 1 recites “a wiring layer where first wiring configured to supply a power supply voltage to the plurality of pixel circuits is disposed and an area occupied by the first wiring is largest among the plurality of wiring layers” which creates a lack of clarity given that: 1) ‘an area’ is not a clearly defined quantitative measure and so cannot be determined to be the largest in comparison to other such quantities; and 2) this limitation compares the ‘area’ of first wiring to, presumably, an ‘area’ of all the other plurality of wiring layers but it is unclear how such a comparison can be made between two different categories of structures, namely a wiring and a wiring layer. Further, the sixth indented limitation of claim 1 recites “and a wiring layer group where the first wiring is disposed” which creates a lack of clarity given that: 1) it is unclear how the wiring layer group can be disposed where the first wiring is disposed if they are not the same structure; and 2) with the comma preceding this phrase, it is unclear to which other part of claim 1 this sentence fragment is related. Further, the sixth indented limitation of claim 1 recites “the wiring layer group being located between the wiring layer where the area occupied by the first wiring is the largest among the plurality of wiring layers and the second semiconductor layer“ which creates a lack of clarity as to whether the wiring layer group is between the second semi layer and ‘the area of the first wiring’ OR ‘the wiring layer as a whole’. Further, the seventh indented limitation of claim 1 recites “wherein, in a plan view, the first wiring is configured to connect both ends of a region in a first direction and both ends of the region in a second direction intersecting the first direction by combination of the wiring layer group” which creates a lack of clarity as to what is meant by ‘combination of the wiring layer group’ particularly in connection with the connecting of the ends of the region in each direction. Additionally, the sixth and seventh indented limitations of claim 7 recite “a wiring layer group where first wiring configured to supply a power supply voltage to the plurality of pixel circuits is disposed, wherein the wiring layer group includes a first wiring layer and a second wiring layer” which creates a lack of clarity given that, if the wiring layer group includes first wiring, first wiring layer, and second wiring layer, then it’s unclear how these similarly-phrased structural items are the same or different from one another. Further, the eighth and ninth indented limitations of claim 7 recite “wherein, in a plan view, the first wiring on the first wiring layer is not connected to at least both ends of a region in a first direction, the region including each of the plurality of pixel circuits, wherein, in the plan view, the first wiring on the second wiring layer is not connected to at least both ends of the region in a second direction” which creates a lack of clarity given that: 1) the presumed portion of the first wiring disposed upon the first/second wiring layer was not properly introduced and so is unclear what this references; and 2) this limitation states the first wiring is not connected to at least both ends of the region, but then the last limitation states the first wiring is connected to at least both ends of the region, which appear to contradict one another. Finally, the last indented limitation of claim 7 recites “wherein, in the plan view, the first wiring is configured to be connected to both ends of the region in the first direction and both ends of the region in the second direction by combination of the first wiring layer and the second wiring layer” which creates a lack of clarity as to what is meant by ‘combination of the first wiring layer and the second wiring layer’ particularly in connection with the connecting of the ends of the region in each direction.
Claims 2-6 and 8-25 depend from claim 1 and so are rejected on the same grounds.
Additionally, both claims 24 and 25, which include all the elements of the photoelectric conversion apparatus according to claim 1, bring in ‘a signal’ output from the photoelectric conversion apparatus, but nothing in claim 1 clearly outputs a signal. Therefore, claims 24 and 25 lack clarity as to where this signal is generated by the photoelectric conversion apparatus of claim 1.
Despite the numerous areas of the claim set that lack clarity, claims 1-25 will be examined as best understood.
Allowable Subject Matter
Claims 1-25, as best understood in their current form, appear to be allowable subject matter. Beyond Applicant’s own prior art that is already well-cited (e.g. US 2020/0273895 A1 to Sasago et al.), additional prior art patents including US 2015/0115131 A1 to Webster et al., US 2017/0186798 A1 to Yang et al., and US 2018/0090536 A1 to Mandai et al. each disclose the majority of independent claims 1 and 7 with respect to the structure containing the stacked APD, the pad, and the pixel circuit substrate.
Specifically, these references disclose “a first substrate including a first semiconductor layer and a first wiring structure, the first semiconductor layer including a plurality of photoelectric conversion units, the first wiring structure including at least one wiring layer; and a second substrate including a second semiconductor layer and a second wiring structure, the second semiconductor layer including a plurality of pixel circuits disposed to correspond to each of the plurality of photoelectric conversion units, respectively, the second wiring structure including a plurality of wiring layers, wherein each of the plurality of photoelectric conversion units includes an avalanche photodiode, wherein the first substrate and the second substrate are stacked such that the first wiring structure and the second wiring structure are located between the first semiconductor layer and the second semiconductor layer, wherein the first wiring structure or the second wiring structure includes a pad electrode configured to supply a voltage to the avalanche photodiode” of claim 1 and similar limitations of claim 7.
However, these references appear to fail to disclose, as best understood, the limitations including “wherein the plurality of wiring layers of the second wiring structure includes a wiring layer where first wiring configured to supply a power supply voltage to the plurality of pixel circuits is disposed and an area occupied by the first wiring is largest among the plurality of wiring layers, and a wiring layer group where the first wiring is disposed, the wiring layer group being located between the wiring layer where the area occupied by the first wiring is the largest among the plurality of wiring layers and the second semiconductor layer, and wherein, in a plan view, the first wiring is configured to connect both ends of a region in a first direction and both ends of the region in a second direction intersecting the first direction by combination of the wiring layer group, the region including each of the plurality of pixel circuits” of claim 1 and similar limitations of claim 7.
Moreover, US 2013/0063203 A1 to Utsumi et al. and US 2018/0240825 A1 to Uesaka et al. each appear to disclose, as best understood, the limitations including “the wiring layer group being located between the wiring layer and the second semiconductor layer, and wherein, in a plan view, the first wiring is configured to connect both ends of a region in a first direction and both ends of the region in a second direction intersecting the first direction by combination of the wiring layer group, the region including each of the plurality of pixel circuits” of claim 1 and similar limitations of claim 7.
However, these references appear to fail to disclose, as best understood, the limitations including “wherein the plurality of wiring layers of the second wiring structure includes a wiring layer where first wiring configured to supply a power supply voltage to the plurality of pixel circuits is disposed and an area occupied by the first wiring is largest among the plurality of wiring layers, and a wiring layer group where the first wiring is disposed, the wiring layer group being located between the wiring layer where the area occupied by the first wiring is the largest among the plurality of wiring layers and the second semiconductor layer” of claim 1 and similar limitations of claim 7.
Examiner again notes that, after amendment is made to claims 1 and 7 to overcome the 35 USC 112 rejection, additional search and consideration will be necessary before making a final determination as to the allowability of independent claims 1 and 7.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF NATALINI can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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