DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-8, and 10- 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (U.S. 2021/0305456 A1, hereinafter refer to Chen).
Regarding Claim 1: Chen discloses a light emitting diode (see Chen, Fig.1B as shown below and ¶ [0002]), comprising:
PNG
media_image1.png
685
739
media_image1.png
Greyscale
PNG
media_image2.png
402
501
media_image2.png
Greyscale
a semiconductor stack (102/103/104), wherein the semiconductor stack (102/103/104) comprises a first semiconductor layer (102), a light emitting layer (103), and a second semiconductor layer (104) stacked in sequence, the semiconductor stack (102/103/104) has a terrace (b1), and the terrace (b1) is an upper surface of the first semiconductor layer (102) which is not covered by the light emitting layer (103) (see Chen, Fig.1B as shown above);
a first electrode (105), located on the terrace (b1) and electrically connected to the first semiconductor layer (102) (see Chen, Fig.1B as shown above);
a second electrode (106), electrically connected to the second semiconductor layer (104) (see Chen, Fig.1B as shown above);
wherein the semiconductor stack (102/103/104) has a first inclined sidewall, two ends of the first inclined sidewall are respectively connected to an upper surface of the second semiconductor layer (104) and the terrace (b1) (see Chen, Fig.1B as shown above),
an included angle (180o- θ1) between the first inclined sidewall and the terrace (b1) is in a range of 110o to 135o (180o- θ1 = (180o- (larger than or equal to 55°) = equal to or smaller than 125o)) (see Chen, Fig.1B as shown above and ¶ [0019]), and
an interval (d1) between the first electrode (105) and the light emitting layer (103) is in a range of 2.5 µm to 13 µm (between 3 μm and 10 μm) (see Chen, Fig.1B as shown above and ¶ [0018]).
Regarding Claim 2: Chen discloses a light emitting diode as set forth in claim 1 as above. Chen further teaches wherein the semiconductor stack (102/103/104) further has a second inclined side wall, two ends of the second inclined side wall are respectively connected to a lower surface of the first semiconductor layer (102) and the terrace (b1), and an included angle (180o- θ2) between the second inclined side wall and the terrace (b1) is in a range of 95o to 105o (180o- θ2 = (180o- (larger than or equal to 75o) = equal to or smaller than 105o)) (see Chen, Fig.1B as shown above and ¶ [0019]).
Regarding Claim 4: Chen discloses a light emitting diode as set forth in claim 1 as above. Chen further teaches wherein the light emitting diode (30) further comprises a substrate (300), an insulating layer (107), a first pad (108), and a second pad (109), the semiconductor stack (102/103/104) is disposed on the substrate (300), the insulating layer (107) covers the semiconductor stack (102/103/104), the first electrode (105), and the second electrode (106), the insulating layer (107) has a first opening (107a) and a second opening (107b), the first pad (108) is disposed on the insulating layer (107), the first pad (108) is connected to the first electrode (105) via the first opening (107a), the second pad (109) is disposed on the insulating layer (107), and the second pad (109) is connected to the second electrode (106) via the second opening (107b) (see Chen, Fig.3 as shown above).
Regarding Claim 5: Chen discloses a light emitting diode as set forth in claim 1 as above. Chen further teaches wherein a vertical distance (d2) between the upper surface of the second semiconductor layer (104) and the terrace (b1) is greater than 10 µm (less than or equal to 10 μm) (see Chen, Fig.1B as shown above and ¶ [0022]).
Regarding Claim 6: Chen discloses a light emitting diode as set forth in claim 1 as above. Chen further teaches wherein the first inclined sidewall is formed by a positive photoresist process in combination with an inductively coupled plasma (ICP) etching process (see Chen, Fig.1B as shown above).
Note: patentability of a product does not depend on its method of production.
Regarding Claim 7: Chen discloses a light emitting diode as set forth in claim 6 as above. Chen further teaches wherein a carrier plate used in the ICP etching process is a metal carrier plate, and a plurality of through holes are formed on the metal carrier plate (see Chen, Fig.1B as shown above).
Note: patentability of a product does not depend on its method of production.
Regarding Claim 8: Chen discloses a light emitting diode as set forth in claim 1 as above. Chen further teaches wherein the first inclined sidewall is formed by one step of a preparation process (see Chen, Fig.1B as shown above).
Note: patentability of a product does not depend on its method of production.
Regarding Claim 10: Chen discloses a light emitting diode as set forth in claim 1 as above. Chen further teaches wherein the light emitting diode (10) is a flipped structure (see Chen, Fig.1B as shown above and Fig.6A).
Regarding Claim 11: Chen discloses a light emitting diode as set forth in claim 1 as above. Chen further teaches wherein the light emitting diode is a red light emitting diode (see Chen, Fig.1B as shown above and ¶ [0025]).
Regarding Claim 12: Chen discloses a light emitting diode as set forth in claim 1 as above. Chen further teaches a light emitting device, comprising the light emitting diode according to claim 1 (see Chen, Fig.1B as shown above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (U.S. 2021/0305456 A1, hereinafter refer to Chen) as applied to claim 1 above, and further in view of Chang et al. (U.S. 2023/0077761 A1, hereinafter refer to Chang).
Regarding Claim 3: Chen discloses a light emitting diode as applied to claim 1 above. Chen is silent upon explicitly disclosing wherein an interval between the second electrode and the first inclined sidewall is greater than or equal to 3 µm.
For support see Chang, which teaches wherein an interval (D5) between the second electrode (50) and the first inclined sidewall is greater than or equal to 3 µm (greater than 1 μm and less than 10 μm) (see Chang, Fig.12 as shown below and ¶ 0068]).
PNG
media_image3.png
337
534
media_image3.png
Greyscale
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Chen and Chang to enable the recited ranges of interval between the second electrode and the first inclined sidewall as taught by Chang in order to control the driving voltage of the light-emitting device and prevent an electrostatic breakdown at an edge of the light-emitting device.
Regarding Claim 9: Chen discloses a light emitting diode as applied to claim 1 above. Chen is silent upon explicitly disclosing wherein the first semiconductor layer is an N-type semiconductor layer, and the second semiconductor layer is a P-type semiconductor layer.
For support see Chang, which teaches wherein the first semiconductor layer (21) is an N-type semiconductor layer, and the second semiconductor layer (23) is a P-type semiconductor layer (see Chang, Fig.12 as shown above, ¶ [0004], ¶ [0036], and ¶ 0038]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Chen and Chang to enable the first semiconductor layer to be an N-type semiconductor layer and the second semiconductor layer to be a P-type semiconductor layer as taught by Chang in order to obtain a light-emitting device with high reliability.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BITEW A DINKE/Primary Examiner, Art Unit 2812