DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 17/755142 (Now U.S. Patent No. 12027989 B2), filed on 04/21/2022.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 08/11/25, 06/10/25, 01/16/25, 07/01/24 and 07/01/24 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the claim limitation of claim 4 reciting that the input rectifier is a half wave rectifier must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 14-16 objected to because of the following informalities:
Claim 14, lines 2-3, recites “an AC-DC converter circuit according to claim 1” which should be changed to “the AC-DC converter circuit according to claim 1”.
Claim 15, line 6, recites “an AC-DC converter circuit according to claim 1” which should be changed to “an AC-DC converter circuit according to claim 1”.
Claim 16, line 2, recites “the first transistor is arranged in arranged an always ON state” should be changed to “the first transistor is arranged to be in an always ON state”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5, 9 and 12-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 5, claim 5 recites, inter alia, “wherein the input rectifier is a full-wave rectifier comprising at least two diodes, and wherein the input rectifier further comprises a third node, wherein the input rectifier is configured to receive an AC voltage between the first node and the third node.” This claim is indefinite because claim 4, from which claim 5 depends upon, recites that the input rectifier is a half wave rectifier while claim 5 essentially changes that structure to a full wave rectifier which is not possible if it is already established to be a half wave rectifier. The Application’s Specification in Paragraph 0056 recites “The input rectifier 110 may be a half-wave or full-wave rectifier” which means that is either one or the other. For purposes of examination the Examiner believes the Applicant meant for claim 5 to be dependent upon claim 1 and thus has interpreted claim 5 to be dependent upon claim 1 instead of claim 4.
Regarding claim 9, claim 9 recites, inter alia, “wherein the output rectifier is a gallium nitride diode, and wherein any diodes of the input rectifier, if present, are gallium nitride diodes.” The claim is indefinite because of the language of “if present” which is not concrete language and leads to ambiguity. Claim 1 presents that an input rectifier is there and claim 9 seems to point to the opposite and that it is a removable portion of the claim. For purposes of examination the Examiner has taken the interpretation that the “if present” will be ignored when examining claim 9.
Regarding claim 12, claim 12 depends upon claim 1 and recites “wherein the first carrier layer structure is connected to the second carrier layer structure, and wherein the first barrier layer structure is connected to the second barrier layer structure.” This language is indefinite due to the fact that claim 1 never recites any language regarding a first carrier layer, a second carrier layer, a first barrier layer and a second barrier layer. Also, this claim does not define where these layers are while being dependent upon claim 1 and furthermore does not define which components are associated with these layers from claim 1. Based on reasoning it seems claim 12 was supposed to be dependent upon claim 10 which does recite these structures in great detail. However, for purposes of thorough examination and giving the claims the broadest reasonable interpretation the Examiner has interpreted claim 12 as reciting that the first transistor has a first carrier layer structure and a first barrier layer structure and the second transistor has a second carrier layer structure and a second barrier layer structure wherein the first carrier layer structure is connected to the second carrier layer structure, and wherein the first barrier layer structure is connected to the second barrier layer structure.
Regarding claim 13, claim 13 recites, inter alia, “wherein the AC-DC converter device further comprises: an interface for receiving an AC voltage from an AC voltage source; and an interface for providing a DC voltage to an electrical battery, wherein the electrical battery is an electrical battery of an electronic vehicle or an electrical battery of a mobile electronic device.” This claim is indefinite because it is not clear whether the components being recited in claim 13 are the same components being recited in claim 1 upon which claim 13 depends upon. Claim 1 recites “an AC voltage” and “an electrical battery” which are the same components being recited in claim 13 without the proper antecedent basis leading to confusion on whether this component is the same component or a different one. Based on the specification (See Paragraphs 0108-0109) of the Application it seems that these Components are one in the same. Therefore, for purposes of examination the Examiner has taken the interpretation that the AC voltage and the Electrical Battery recited in claims 1 and 13 are the same.
Regarding claim 14, claim 14 recites, inter alia, “a method for charging an electrical battery of an electric vehicle comprising, in addition to the electrical battery, a traction motor and an AC-DC converter circuit according to claim 1, the method comprising: decelerating a motion of the electric vehicle; generating an AC type current from said traction motor by the deceleration of the motion of the electric vehicle; converting the generated AC type current to a DC type current by the AC-DC converter circuit; and charging the electrical battery with the DC type current.” This claim is indefinite due the claim not being clear whether the components being recited in claim 14 are the same components being recited in claim 1 upon which claim 14 depends upon. Claim 1 recites “an electrical battery” while claim 14 also recites the same component without the proper antecedent basis leading to confusion on whether this component is the same component or a different one. Based on the specification (See Paragraphs 0108-0109) of the Application it seems that these Components are one in the same. Therefore, for purposes of examination the Examiner has taken the interpretation that the Electrical Battery recited in claims 1 and 14 are the same.
Regarding claim 15, claim 15 recites, inter alia, “A regenerative braking system of an electric vehicle, the regenerative braking system comprising: an electrical battery”. This claim is indefinite due the claim not being clear whether the components being recited in claim 15 are the same components being recited in claim 1 upon which claim 15 depends upon. Claim 1 recites “an electrical battery” while claim 15 also recites the same component without the proper antecedent basis leading to confusion on whether this component is the same component or a different one. Based on the specification (See Paragraphs 0108-0109) of the Application it seems that these Components are one in the same. Therefore, for purposes of examination the Examiner has taken the interpretation that the Electrical Battery recited in claims 1 and 15 are the same.
Claim Rejections
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-8, 12-13 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Ernoux (US 2010/0259186 A1) in view of Imada (US 2013/0187627 A1) in further view of Deboy (US 2015/0263100 A1).
Regarding claim 1, Ernoux teaches an AC-DC converter circuit (Figure 2 Components 208+212 or Figure 2 Component 200) for high power charging of a load (Figure 2 Component 205), the AC-DC converter circuit comprising: an input rectifier (Figure 2 Component 208) comprising a first node (Figure 2 Component 216) and a second node (Figure 2 Component 242), wherein the input rectifier is configured to receive an AC voltage (Figure 2 Component 202) at the first node (Figure 2 Component 216/236 receives the AC voltage) and provide a rectified voltage at the second node (Figure 2 Component 242 receives the rectified voltage); a first transistor (Figure 2 Component 222 is seen in greater detail in Figure 3; Figure 3 Component 303; Paragraph 0028 “FIG. 3 can be optimized for a high switching speed and can be utilized for fast III-nitride switch 122 in FIG. 1 or fast III-nitride switch 222 in FIG. 2”), the first transistor being a depletion type transistor (Paragraph 0028 “D-mode III-nitride device 303”; Paragraph 0018 points out D-mode means depletion mode) and comprising a first gate node, a first source node, and a first drain node (Figure 3 Component 303 has a drain, source and gate terminal), wherein the first drain node is connected to the second node of the input rectifier (Paragraph 0030 “drain of D-mode III-nitride device 303 is coupled to terminal 313”; Figure 3 Component 313 is the top terminal of Component 222 seen in Figure 2; Figure 2 Component 222 top terminal receives the rectified voltage from Component 242), and wherein the first gate node is connected so that it turns ON/OFF with a second transistor (Figure 3 Component 303 has a gate connected to the source terminal of Component 307 to always follow the operation of that switch); a second transistor (Figure 3 Component 307), comprising a second gate node, a second source node, and a second drain node (Figure 3 Component 307 has a gate, drain and source terminal), wherein the second drain node is connected to the first source node (Figure 3 Component 307 has a drain terminal connected to the source terminal of Component 303), wherein the second transistor materially corresponds to the first transistor (Figure 3 Components 303 and 307 are materially III-nitride switches indicating that both are nitride compound semiconductors); a duty cycle control unit (Figure 2 Component 220) connected to the second gate node for providing the second transistor with a switching waveform (Figure 3 Component 307 has a gate terminal receiving a signal to control the switch and the signal comes from the controller 220 shown in Figure 2); an output rectifier (Figure 2 Component 224; Component 224 is seen in further detail in Figure 4; Paragraph 0033 “low resistance switch 424 can be optimized for low on-state resistance and utilized for low resistance switch 124 in buck converter 112 in FIG. 1 or for low resistance switch 224 in buck converter 212 in FIG. 2”; Figure 4 shows a diode and a transistor and each can be seen as a rectifier; For reference Applicant’s own Figure 2 shows component 150 as the output rectifier and Ernoux shows the same configuration); and an output electronic filter (Figure 2 Component 226); wherein the output rectifier and the output electronic filter are both connected to the second source node forming a buck topology (Figure 2 shows that both the output rectifier and the filter are connected to the bottom terminal of Component 222 which as seen in Figure 3 is the source terminal of Component 307 and by this connection form a buck converter; Title “Buck Converter With III-nitride Switch”), or the output rectifier is connected to the first source node and the output electronic filter is connected to the second source node and an output node of the output rectifier forming a boost topology (This limitation is an ‘or’ limitation so does not have to be met by the prior art since the last limitation regarding a buck converter was met; However, a simple change from a buck converter to a boost converter is well known in the art as it is simply placing the inductor at the input).
Ernoux does not teach wherein the load is an electrical battery; and wherein the first gate node is connected to a ground node.
Imada teaches an AC/DC converter (Figure 10), comprising: an AC source (Figure 10 Component 200); an input rectifier (Figure 10 Component 210); a first transistor having a gate, source and drain terminal (Figure 10 Component 10A is seen in more detail in Figure 2; Figure 2 Component 30 which has a gate, source and drain terminal), wherein the gate terminal is connected to ground and the gate node of the first transistor is arranged in arranged an always ON state (Figure 2 Component 30 is a depression type GaN-HEMT and is grounded thus is always ON); a second transistor having a gate, source and drain terminal (Figure 2 Component 20).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Ernoux to incorporate grounding the gate of the first transistor as taught by Imada. The advantage of this design is that it becomes an always-on element so that all the switching timing is determined by one transistor thus eliminating any delays while also simplifying the switching scheme leading to more efficient switching.
Deboy teaches a power circuit (Figures 1-3 and 9B), comprising: a power circuit (Figure 1 Component 6) that provides for a load wherein the load is an electrical battery (Paragraph 0037 “Numerous examples of load 4 exist and may include, but are not limited to, computing devices and related components, such as microprocessors, electrical components, circuits, laptop computers, desktop computers, tablet computers, mobile phones, batteries, speakers, lighting units, automotive/marine/aerospace/train related components, motors, transformers, or any other type of electrical device and/or circuitry that receives a voltage or a current from a power converter”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Ernoux to incorporate having the load be an electrical battery for a mobile device or automotive as taught by Deboy. The advantage of this design is that the power converter designed by Ernoux can be utilized in a system that requires a high voltage from an AC source thus giving utility to the converter proposed by Ernoux.
Regarding claim 2, Ernoux, Imada and Deboy teach all the limitations of claim 1. Ernoux further teaches wherein the first transistor is a high-electron-mobility transistor, HEMT, and wherein the second transistor is a HEMT (Paragraph 0001 highlights that III-nitride switches are GaN HEMT switches; Paragraph 0028 “D-mode III-nitride device 303”; Although the reference does not expressly use the term “HEMT”, the GaN switches disclosed therein are understood to be GaN HEMT devices, as lateral AlGaN/GaN HEMTs were the only practical GaN power transistors available for high frequency power conversion at that time; Also for reference Imada the secondary reference does use the term HEMT).
Regarding claim 3, Ernoux, Imada and Deboy teach all the limitations of claim 1. Ernoux further teaches wherein the first transistor is a gallium nitride transistor (Paragraph 0001 highlights that III-nitride switches are GaN HEMT switches; Paragraph 0028 “D-mode III-nitride device 303”).
Ernoux does not teach wherein the second transistor is a gallium nitride transistor.
Deboy teaches a power circuit (Figures 1-3 and 9B), comprising: a power circuit (Figure 1 Component 6), wherein the power circuit comprises: a first transistor (Figure 1 Component 32A) and a second transistor (Figure 3 Component 32B); wherein the first transistor is a gallium nitride transistor the second transistor is a gallium nitride transistor (Paragraph 0064 “GaN bidirectional switches 32A, 32B”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Ernoux to incorporate having the second switch also be a gallium nitride transistor as taught by Deboy. The advantage of this design is that it reduces switching and reverse recovery losses while improving transient matching with the ground gated Gallium Nitride top transistor thus enabling higher efficiency operation.
Regarding claim 5 (See 112(b) Rejection), Ernoux, Imada and Deboy teach all the limitations of claim 1 (Please Refer to the 112(b) Rejection above for the interpretation of why Claim 5 is put under this header instead of being dependent upon claim 4; The claim 4 dependent rejection can be found below). Ernoux further teaches wherein the input rectifier is a full-wave rectifier comprising at least two diodes (Figure 2 Component 208), and wherein the input rectifier further comprises a third node, wherein the input rectifier is configured to receive an AC voltage between the first node and the third node (Figure 2 Component 236).
Regarding claim 6, Ernoux, Imada and Deboy teach all the limitations of claim 1. Ernoux further teaches a control circuit (Figure 2 Component 220) for monitoring the output voltage level, wherein the control circuit is configured to provide feedback to the duty cycle control unit based on the monitored output voltage level (Paragraph 0027 “control circuit 220 can be configured to control the respective duty cycles of fast III-nitride switch 222 and low resistance switch 224 so to appropriately adjust the output voltage (i.e. Vout 252) in response to a feedback signal provided at node 250”).
Regarding claim 7, Ernoux, Imada and Deboy teach all the limitations of claim 1. Ernoux does not teach wherein the first transistor and the second transistor are integrated monolithically on a same substrate layer structure.
Deboy teaches a power circuit (Figures 1-3 and 9B), comprising: a power circuit (Figure 1 Component 6), wherein the power circuit comprises: a first transistor (Figure 1 Component 32A) and a second transistor (Figure 3 Component 32B), wherein the first transistor is a gallium nitride transistor the second transistor is a gallium nitride transistor (Paragraph 0064 “GaN bidirectional switches 32A, 32B”), wherein the first transistor and the second transistor are integrated monolithically on a same substrate layer structure (Figure 9B shows the semiconductor body of the gallium nitride switches), wherein the substrate layer structure comprises a silicon substrate layer (Figure 9B Component 114; Paragraph 0159 “wherein the common substrate comprises a silicon substrate”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Ernoux to incorporate having both switches be gallium nitride switches integrated monolithically as taught by Deboy. The advantage of this design is that the common substrate reduces parasitic inductances and capacitance between the devices and improves the switching and voltage sharing capabilities.
Regarding claim 8, Ernoux, Imada and Deboy teach all the limitations of claim 7. Ernoux does not teach wherein the substrate layer structure comprises a silicon substrate layer.
Deboy teaches a power circuit (Figures 1-3 and 9B), comprising: a power circuit (Figure 1 Component 6), wherein the power circuit comprises: a first transistor (Figure 1 Component 32A) and a second transistor (Figure 3 Component 32B), wherein the first transistor is a gallium nitride transistor the second transistor is a gallium nitride transistor (Paragraph 0064 “GaN bidirectional switches 32A, 32B”), wherein the first transistor and the second transistor are integrated monolithically on a same substrate layer structure (Figure 9B shows the semiconductor body of the gallium nitride switches), wherein the substrate layer structure comprises a silicon substrate layer (Figure 9B Component 114; Paragraph 0159 “wherein the common substrate comprises a silicon substrate”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Ernoux to incorporate having both switches be gallium nitride switches integrated monolithically as taught by Deboy. The advantage of this design is that the common substrate reduces parasitic inductances and capacitance between the devices and improves the switching and voltage sharing capabilities.
Regarding claim 12 (See 112(b) Rejection), Ernoux, Imada and Deboy teach all the limitations of claim 1. Ernoux does not teach wherein the first carrier layer structure is connected to the second carrier layer structure, and wherein the first barrier layer structure is connected to the second barrier layer structure.
Deboy teaches a power circuit (Figures 1-3 and 9B), comprising: a power circuit (Figure 1 Component 6), wherein the power circuit comprises: a first transistor (Figure 1 Component 32A) and a second transistor (Figure 3 Component 32B), wherein the first transistor is a gallium nitride transistor the second transistor is a gallium nitride transistor (Paragraph 0064 “GaN bidirectional switches 32A, 32B”), wherein the first transistor and the second transistor are integrated monolithically on a same substrate layer structure (Figure 9B shows the semiconductor body of the gallium nitride switches), wherein the first transistor comprises a first carrier layer structure (Figure 9B Component 118A) above a substrate layer structure (Figure 9B Component 112) and a first barrier layer structure above the first carrier layer structure (Figure 9B Component 120A/122A); wherein the second transistor comprises a second carrier layer structure (Figure 9B Component 118B) above the substrate layer structure (Figure 9B Component 112) and a second barrier layer structure above the second carrier layer structure (Figure 9B Component 120B/122B); wherein the first carrier layer structure is connected to the second carrier layer structure (Figure 9B Component 118A and 118B are connected through the intrinsic capacitance Component 130), and wherein the first barrier layer structure is connected to the second barrier layer structure (Figure 9B Component 120B and 120A are connected through the intrinsic capacitance Component 130).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Ernoux to incorporate having both switches be gallium nitride switches integrated monolithically as taught by Deboy. The advantage of this design is that the common substrate reduces parasitic inductances and capacitance between the devices and improves the switching and voltage sharing capabilities.
Regarding claim 13 (See 112(b) Rejection), Ernoux, Imada and Deboy teach all the limitations of claim 1. Ernoux further teaches an AC-DC converter device (Figure 2 as a whole can be seen as an AC/DC converter device) comprising the AC-DC converter circuit (Figure 2 Components 208+212 or Component 200) according to claim 1, wherein the AC-DC converter device further comprises: an interface for receiving an AC voltage (Figure 2 Component 206; Interface can broadly be defined as a point where two systems or components meet; The EMI filter allows the connection of the AC source to the rectifier thus can be referred to as an interface) from an AC voltage source (Figure 2 Components 202); and an interface for providing a DC voltage to a load (Figure 2 Component 205 is a load connection thus can be seen as an interface).
Ernoux does not teach providing the DC voltage to an electrical battery, wherein the electrical battery is an electrical battery of an electronic vehicle or an electrical battery of a mobile electronic device.
Deboy teaches a power circuit (Figures 1-3 and 9B), comprising: a power circuit (Figure 1 Component 6) that provides for a load wherein the load is an electrical battery of an electronic vehicle or an electrical battery of a mobile electronic device (Paragraph 0037 “Numerous examples of load 4 exist and may include, but are not limited to, computing devices and related components, such as microprocessors, electrical components, circuits, laptop computers, desktop computers, tablet computers, mobile phones, batteries, speakers, lighting units, automotive/marine/aerospace/train related components, motors, transformers, or any other type of electrical device and/or circuitry that receives a voltage or a current from a power converter”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Ernoux to incorporate having the load be an electrical battery for a mobile device or automotive as taught by Deboy. The advantage of this design is that the power converter designed by Ernoux can be utilized in a system that requires a high voltage from an AC source thus giving utility to the converter proposed by Ernoux.
Regarding claim 16, Ernoux, Imada and Deboy teach all the limitations of claim 1. Ernoux does not teach wherein the first gate node of the first transistor is arranged in arranged an always ON state.
Imada teaches an AC/DC converter (Figure 10), comprising: an AC source (Figure 10 Component 200); an input rectifier (Figure 10 Component 210); a first transistor having a gate, source and drain terminal (Figure 10 Component 10A is seen in more detail in Figure 2; Figure 2 Component 30 which has a gate, source and drain terminal), wherein the gate terminal is connected to ground and the gate node of the first transistor is arranged in arranged an always ON state (Figure 2 Component 30 is a depression type GaN-HEMT and is grounded thus is always ON); a second transistor having a gate, source and drain terminal (Figure 2 Component 20).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Ernoux to incorporate grounding the gate of the first transistor as taught by Imada. The advantage of this design is that it becomes an always-on element so that all the switching timing is determined by one transistor thus eliminating any delays while also simplifying the switching scheme leading to more efficient switching.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Ernoux (US 2010/0259186 A1) in view of Imada (US 2013/0187627 A1) in further view of Deboy (US 2015/0263100 A1) and Li (US 2020/0112202 A1).
Regarding claim 4, Ernoux, Imada and Deboy teach all the limitations of claim 1. Ernoux further teaches wherein the input rectifier comprises at least one diode (Figure 2 Component 208).
Ernoux does not teach wherein the input rectifier is a half-wave rectifier.
Li teaches a power converter (Figure 2), comprising: a rectifier circuit (Figure 2 Component 112) wherein the rectifier circuit can be a half-wave rectifier instead of a full wave rectifier (Paragraph 0056 “the description is based upon a full-wave rectifier (e.g., full-wave rectifier 112 shown in FIG. 3), the implementation of the power receiver 120 shown in FIG. 3 may have many variations, alternatives, and modifications. For example, half-wave rectifiers may be alternatively employed”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Ernoux to incorporate using a half wave rectifier as taught by Li. The benefit of this design is that it simplifies the overall circuit design and also lowers the cost of the overall circuit design production.
Regarding claim 5 (See 112(b) Rejection), Ernoux, Imada, Deboy and Li teach all the limitations of claim 4. Ernoux further teaches wherein the input rectifier is a full-wave rectifier comprising at least two diodes (Figure 2 Component 208), and wherein the input rectifier further comprises a third node, wherein the input rectifier is configured to receive an AC voltage between the first node and the third node (Figure 2 Component 236).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Ernoux (US 2010/0259186 A1) in view of Imada (US 2013/0187627 A1) in further view of Deboy (US 2015/0263100 A1) and Yanagihara (US 7375407 B2).
Regarding claim 9, Ernoux, Imada and Deboy teach all the limitations of claim 1. Ernoux further teaches wherein the output rectifier is a gallium nitride diode (Paragraph 0033 “D-mode III-nitride device 403”; Paragraph 0001).
Ernoux does not teach wherein any diodes of the input rectifier, if present, are gallium nitride diodes.
Yanagihara teaches an AC/DC converter (Figure 8), comprising: an input rectifier made up of diodes (Figure 8 Components 21A-21D) wherein the diodes of the input rectifier are gallium nitride diodes (Col. 4 Lines 50-67 explain how the diodes shown in Figure 8 are made and gallium nitride are the elements used in its construction).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Ernoux to incorporate having gallium nitride diodes at the input rectifier circuit as taught by Yanagihara. The advantage of this design is that the diodes attain a high breakdown voltage and a low on resistance enabling higher frequency operation with reduced switching loses and improved efficiency.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-9 and 12-15 of U.S. Patent No. 12027989 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of U.S. Patent No. 12027989 B2 anticipate the claims of the immediate application.
Regarding claim 1, U.S. Patent No. 12027989 B2 teaches all the limitations of claim 1, see U.S. Patent No. 12027989 B2 Claim 1 (Col. 19 Lines 39-67).
Regarding claim 2, U.S. Patent No. 12027989 B2 teaches all the limitations of claim 1 and further teaches all the limitations of claim 2 see U.S. Patent No. 12027989 B2 Claim 2.
Regarding claim 3, U.S. Patent No. 12027989 B2 teaches all the limitations of claim 1 and further teaches all the limitations of claim 3 see U.S. Patent No. 12027989 B2 Claim 3.
Regarding claim 4, U.S. Patent No. 12027989 B2 teaches all the limitations of claim 1 and further teaches all the limitations of claim 4 see U.S. Patent No. 12027989 B2 Claim 4.
Regarding claim 5, U.S. Patent No. 12027989 B2 teaches all the limitations of claim 4 and further teaches all the limitations of claim 5 see U.S. Patent No. 12027989 B2 Claim 5.
Regarding claim 6, U.S. Patent No. 12027989 B2 teaches all the limitations of claim 1 and further teaches all the limitations of claim 6 see U.S. Patent No. 12027989 B2 Claim 6.
Regarding claim 7, U.S. Patent No. 12027989 B2 teaches all the limitations of claim 1 and further teaches all the limitations of claim 7 see U.S. Patent No. 12027989 B2 Claim 7.
Regarding claim 8, U.S. Patent No. 12027989 B2 teaches all the limitations of claim 7 and further teaches all the limitations of claim 8 see U.S. Patent No. 12027989 B2 Claim 8.
Regarding claim 9, U.S. Patent No. 12027989 B2 teaches all the limitations of claim 1 and further teaches all the limitations of claim 9 see U.S. Patent No. 12027989 B2 Claim 9.
Regarding claim 10, U.S. Patent No. 12027989 B2 teaches all the limitations of claim 1 and further teaches all the limitations of claim 10 see U.S. Patent No. 12027989 B2 Claim 1 (Col. 20 Lines 1-20).
Regarding claim 11, U.S. Patent No. 12027989 B2 teaches all the limitations of claim 10 and further teaches all the limitations of claim 11 see U.S. Patent No. 12027989 B2 Claim 1 (Col. 20 Lines 21-24).
Regarding claim 12, U.S. Patent No. 12027989 B2 teaches all the limitations of claim 1 and further teaches all the limitations of claim 12 see U.S. Patent No. 12027989 B2 Claim 12.
Regarding claim 13, U.S. Patent No. 12027989 B2 teaches all the limitations of claim 1 and further teaches all the limitations of claim 13 see U.S. Patent No. 12027989 B2 Claim 13.
Regarding claim 14, U.S. Patent No. 12027989 B2 teaches all the limitations of claim 1 and further teaches all the limitations of claim 14 see U.S. Patent No. 12027989 B2 Claim 14.
Regarding claim 15, U.S. Patent No. 12027989 B2 teaches all the limitations of claim 1 and further teaches all the limitations of claim 15 see U.S. Patent No. 12027989 B2 Claim 15.
Claim 16 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12027989 B2 in view of Imada (US 2013/0187627 A1).
Regarding claim 16, U.S. Patent No. 12027989 B2 teaches all the limitations of claim 1, however, the claims of U.S. Patent No. 12027989 B2 does not teach wherein the first gate node of the first transistor is arranged in arranged an always ON state.
Imada teaches an AC/DC converter (Figure 10), comprising: an AC source (Figure 10 Component 200); an input rectifier (Figure 10 Component 210); a first transistor having a gate, source and drain terminal (Figure 10 Component 10A is seen in more detail in Figure 2; Figure 2 Component 30 which has a gate, source and drain terminal), wherein the gate terminal is connected to ground and the gate node of the first transistor is arranged in an always ON state (Figure 2 Component 30 is a depression type GaN-HEMT and is grounded thus is always ON); a second transistor having a gate, source and drain terminal (Figure 2 Component 20).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of the claims of U.S. Patent No. 12027989 B2 to incorporate grounding the gate of the first transistor as taught by Imada. The advantage of this design is that it becomes an always-on element so that all the switching timing is determined by one transistor thus eliminating any delays while also simplifying the switching scheme leading to more efficient switching.
Allowable Subject Matter
Claims 10-11 are rejected under double patenting above, however, no prior art rejection could be made for the limitations recited in claims 10 and 11 therefore claims 10 and 11 would be allowable if rewritten to overcome the double patenting rejection, or have a terminal disclaimer filed (However the language must differ otherwise a statutory double patenting may be presented), and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 10, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests wherein the nodes of the first transistor are physically separated by first spacer structures; wherein the nodes of the second transistor are physically separated by second spacer structures. Claim 11 depends upon claim 10.
Claims 14-15 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims AND rewritten to overcome the double patenting rejection, or have a terminal disclaimer filed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 14, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests decelerating a motion of the electric vehicle; generating an AC type current from said traction motor by the deceleration of the motion of the electric vehicle; converting the generated AC type current to a DC type current by the AC-DC converter circuit; and charging the electrical battery with the DC type current.
Regarding claim 15, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests a regenerative braking system of an electric vehicle, the regenerative braking system comprising: a braking system adapted for decelerating the electric vehicle; an AC-DC converter circuit according to claim 1 configured to convert an AC type current from the traction motor to a DC type current and charge the electrical battery; and a DC-AC converter circuit configured to convert a DC type current from the electrical battery to an AC type current to power the traction motor.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Green (US 2014/0239346 A1) teaches a semiconductor device includes a substrate comprising a heterostructure configured to support formation of a channel during operation, first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate, a gate supported by the substrate, disposed in a first opening in the first dielectric layer, and to which a bias voltage is applied during operation to control current flow through the channel, the second dielectric layer being disposed between the gate and the substrate, and an electrode supported by the substrate, disposed in a second opening in the first and second dielectric layers, and configured to establish a Schottky junction with the substrate. Green was the closest prior art reference that taught the third spacer structure. Green teaches a semiconductor chip (Figure 1), comprising: a first carrier structure (Figure 1 Component 107 Left); a second carrier structure (Figure 1 Component 107 Right); a first barrier structure (Figure 1 Component 108 Left); a second barrier structure (Figure 1 Component 108 Right); a third spacer structure separating the first structures from the second structures (Figure 1 Component 114). Green also taught the structure of the switch configuration of the first and second transistor (Figure 4).
Lu (US 2019/0238062 A1) teaches a three level rectifier and inverter for an electric vehicle and contains an operational mode for braking regeneration.
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/Shahzeb K Ahmad/Examiner, Art Unit 2838