DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to foreign application TW113100937 filed on 01/09/2024. The foreign application is not in English. The certified copy of the foreign priority application TW113100937 has been received.
Filing Dates for the Claims — All Claims Not Entitled to Priority Date
To be entitled to the filing date of the foreign priority application TW113100937 that is not in English, an English translation of the non-English language foreign application TW113100937 and a statement that the translation is accurate in accordance with 37 CFR 1.55 is required to perfect the claim for priority under 35 U.S.C. 119 (a)-(d). The foreign application must adequately support the claimed subject matter, meaning satisfy the written description and enablement requirements of 35 U.S.C. 112(a). See MPEP §§ 215 and 216. 37 C.F.R. 1.55(g)(3)(ii)-(iii). To demonstrate compliance with 35 U.S.C. 112(a), applicant should point to support for their claimed subject matter in their translations.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 10 are rejected under 35 U.S.C. 102 (a)(1)/(a)(2) as being anticipated by Taguchi (US Pub. 20170278781).
Regarding claim 1, Taguchi discloses in Fig. 1 a semiconductor wiring substrate, comprising:
at least one circuit layer [1b], comprising a plurality of signal traces and a plurality of ground traces, wherein the plurality of signal traces and the plurality of ground traces are alternately arranged on the at least one circuit layer, and the at least one circuit layer has a channel width in a first direction;
at least one dielectric layer [1a], between the at least one circuit layer; and
a redistribution layer, arranged above the at least one circuit layer, configured to allow at least one first solder bump and at least one second solder bump to be placed, and comprising at least one first metal contact and at least one second metal contact, wherein the at least one first solder bump and the at least one second solder bump are electrically connected to the at least one circuit layer through the at least one first metal contact and the at least one second metal contact, respectively, so that the channel width is greater than a first spacing between the at least one first solder bump and the at least one second solder bump in the first direction.
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Regarding claim 2, Taguchi discloses in Fig. 1
wherein the plurality of signal traces each has a signal trace width, the plurality of ground traces each has a ground trace width, and the ground trace width is greater than or equal to the signal trace width [greater].
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Regarding claims 3-4, Taguchi discloses in Fig. 1
wherein the at least one circuit layer [1b] further comprises at least one shielding structure [3P and/or 3G] and at least one third metal contact [3S], the at least one first metal contact and the at least one second metal contact are connected to at least corresponding one of the plurality of signal traces through the at least one third metal contact, and the at least one shielding structure at least partially surrounds the at least one third metal contact.
wherein the at least one shielding structure is a power layout or a ground layout.
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Regarding claim 5, Taguchi discloses in Fig. 1
wherein the first spacing is smaller than a second spacing between the at least one first metal contact and the at least one second metal contact in the first direction.
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Regarding claim 6, Taguchi discloses in Fig. 1 wherein the at least one dielectric layer [1a] has a thickness in a second direction perpendicular to the first direction, the plurality of signal traces each has a signal trace width, one of the plurality of signal traces is spaced at an edge distance from adjacent one of the plurality of ground traces, and the thickness of the at least one dielectric layer [1a] is greater than or equal to the signal trace width and the edge distance.
Regarding claim 10, Taguchi discloses in Fig. 1
a power/ground layout layer, arranged below the at least one circuit layer, and comprising a plurality of power layouts and a plurality of ground layouts.
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US Pub. 20230387030) in view of Taguchi (US Pub. 20170278781).
Regarding claim 1, Yang et al. discloses in Fig. 4, paragraph [0045]-[0054] a semiconductor wiring substrate [400], comprising:
at least one circuit layer [10, 20, 30, 40], comprising a plurality of signal traces [S] and a plurality of ground traces [G], wherein the plurality of signal traces [S] and the plurality of ground traces [G] are alternately arranged on the at least one circuit layer [10, 20, 30 or 40], and the at least one circuit layer [10, 20, 30 or 40] has a channel width in a first direction;
at least one dielectric layer [15, 25 or 35], between the at least one circuit layer [10, 20, 30, 40]; and
Yang et al. fails to disclose
a redistribution layer, arranged above the at least one circuit layer, configured to allow at least one first solder bump and at least one second solder bump to be placed, and comprising at least one first metal contact and at least one second metal contact, wherein the at least one first solder bump and the at least one second solder bump are electrically connected to the at least one circuit layer through the at least one first metal contact and the at least one second metal contact, respectively, so that the channel width is greater than a first spacing between the at least one first solder bump and the at least one second solder bump in the first direction.
Taguchi discloses in Fig. 1
a redistribution layer, arranged above the at least one circuit layer, configured to allow at least one first solder bump and at least one second solder bump to be placed, and comprising at least one first metal contact and at least one second metal contact, wherein the at least one first solder bump and the at least one second solder bump are electrically connected to the at least one circuit layer through the at least one first metal contact and the at least one second metal contact, respectively, so that the channel width is greater than a first spacing between the at least one first solder bump and the at least one second solder bump in the first direction.
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Taguchi into the method of Yang et al. to include a redistribution layer, arranged above the at least one circuit layer, configured to allow at least one first solder bump and at least one second solder bump to be placed, and comprising at least one first metal contact and at least one second metal contact, wherein the at least one first solder bump and the at least one second solder bump are electrically connected to the at least one circuit layer through the at least one first metal contact and the at least one second metal contact, respectively, so that the channel width is greater than a first spacing between the at least one first solder bump and the at least one second solder bump in the first direction. The ordinary artisan would have been motivated to modify Yang et al. in the above manner for the purpose of providing method for forming electrical connection between the wiring substrate and the semiconductor devices.
Regarding claims 2 and 12, Yang et al. discloses in Fig. 4
wherein the plurality of signal traces [S] each has a signal trace width [sw1], the plurality of ground traces [G] each has a ground trace width [gw1], and the ground trace width [gw1] is greater than or equal to the signal trace width [sw1].
Regarding claims 3-4, 13-14, Yang et al. fails to disclose
wherein the at least one circuit layer further comprises at least one shielding structure and at least one third metal contact, the at least one first metal contact and the at least one second metal contact are connected to at least corresponding one of the plurality of signal traces through the at least one third metal contact, and the at least one shielding structure at least partially surrounds the at least one third metal contact;
wherein the at least one shielding structure is a power layout or a ground layout.
Taguchi discloses in Fig. 1
wherein the at least one circuit layer [1b] further comprises at least one shielding structure [3P and/or 3G] and at least one third metal contact [3S], the at least one first metal contact and the at least one second metal contact are connected to at least corresponding one of the plurality of signal traces through the at least one third metal contact, and the at least one shielding structure at least partially surrounds the at least one third metal contact;
wherein the at least one shielding structure is a power layout or a ground layout.
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Taguchi into the method of Yang to include wherein the at least one circuit layer further comprises at least one shielding structure and at least one third metal contact, the at least one first metal contact and the at least one second metal contact are connected to at least corresponding one of the plurality of signal traces through the at least one third metal contact, and the at least one shielding structure at least partially surrounds the at least one third metal contact; wherein the at least one shielding structure is a power layout or a ground layout. The ordinary artisan would have been motivated to modify Yang et al. in the above manner for the purpose of reducing noise interference between the signal through holes [paragraph [0017] of Taguchi].
Regarding claims 5 and 15, Taguchi discloses in Fig. 1
wherein the first spacing is smaller than a second spacing between the at least one first metal contact and the at least one second metal contact in the first direction.
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Regarding claims 6 and 16, Yang et al. discloses in Fig. 4
wherein the at least one dielectric layer [15, 25 or 35] has a thickness in a second direction perpendicular to the first direction, the plurality of signal traces [S] each has a signal trace width [sw1], one of the plurality of signal traces [S] is spaced at an edge distance [ed1] from adjacent one of the plurality of ground traces [G], and the thickness of the at least one dielectric layer [15, 25 or 35] is greater than or equal to the signal trace width [sw1] and the edge distance [ed1].
Regarding claims 7 and 17, Yang et al. discloses in Fig. 4
wherein the at least one circuit layer [10, 20, 30, 40] comprises:
a first circuit layer [10], comprising a plurality of first signal traces, a plurality of first ground traces and a first shielding structure [outermost ground pads], wherein the plurality of first signal traces and the plurality of first ground traces are alternately arranged on the first circuit layer [10], and the first shielding structure [outermost ground pads] is arranged on two opposite sides of the plurality of first signal traces and the plurality of first ground traces which are alternately arranged; and
a second circuit layer [20], arranged below the first circuit layer [10], and comprising a plurality of second signal traces, a plurality of second ground traces and a second shielding structure [outermost ground pads], wherein the plurality of second signal traces and the plurality of second ground traces are alternately arranged on the second circuit layer [20], and the second shielding structure [outermost ground pads] is arranged on two opposite sides of the plurality of second signal traces and the plurality of second ground traces which are alternately arranged;
wherein a distance from an outer edge of one of both the plurality of first signal traces and the plurality of first ground traces, which is the closest to the first shielding structure, to an outer edge of one of both the plurality of second signal traces and the plurality of second ground traces, which is the closest to the second shielding structure, is the channel width.
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Regarding claims 8 and 18, Yang discloses in Fig. 4
wherein the at least one circuit layer [10, 20, 30, 40] further comprises:
a third circuit layer [30], arranged below the second circuit layer [20], and comprising a plurality of third signal traces, a plurality of third ground traces and a third shielding structure [outermost ground pads], wherein the plurality of third signal traces and the plurality of third ground traces are alternately arranged on the third circuit layer [30], and the third shielding structure [outermost ground pads] is arranged on two opposite sides of the plurality of third signal traces and the plurality of third ground traces which are alternately arranged;
wherein the at least one dielectric layer [15, 25, 35] comprises:
a first dielectric layer [15], arranged between the first circuit layer [10] and the second circuit layer [20]; and
a second dielectric layer [25], arranged between the second circuit layer [20] and the third circuit layer [30];
wherein a first projection of one of the plurality of first signal traces on the third circuit layer [30] along a second direction perpendicular to the first direction and one of the plurality of third signal traces are fully overlapped, and a second projection of one of the plurality of first ground traces on the third circuit layer [30] along the second direction and one of the plurality of third ground traces are fully overlapped.
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Regarding claims 9 and 19, Yang et al. discloses in Fig. 4
wherein a first projection of one of the plurality of first signal traces on the second circuit layer [20] along a second direction perpendicular to the first direction and one of the plurality of second ground traces are partially overlapped, and a second projection of one of the plurality of first ground traces on the second circuit layer [20] along the second direction and one of the plurality of second signal traces are partially overlapped.
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Regarding claims 10 and 20, Yang et al. discloses in Fig. 1, paragraph [0046]
wherein the semiconductor wiring substrate [550/400] further comprises:
a power/ground layout layer [60], arranged below the at least one circuit layer, and comprising a plurality of power layouts and a plurality of ground layouts.
Regarding claim 11, Yang et al. discloses in Fig. 4, Fig. 5, paragraph [0048]-[0054] a semiconductor package device, comprising:
a first chip [501];
a second chip [503], configured to perform a transmission of at least one signal with the first chip [501] through at least one channel [CH1-CH4];
a package substrate [507]; and
an interposer [505], comprising a semiconductor wiring substrate [550/400]], a first surface and a second surface, wherein the first surface and the second surface are opposite to each other, the first chip [501] and the second chip [503] are electrically connected to the first surface, and the package substrate [507] is electrically connected to the second surface;
wherein the semiconductor wiring substrate [550/400] comprises:
at least one circuit layer [10, 20, 30, 40], electrically coupled between the first chip [501] and the second chip [503] as the at least one channel, and comprising a plurality of signal traces [S] and a plurality of ground traces [G], wherein the plurality of signal traces [S] and the plurality of ground traces [G] are alternately arranged on the at least one circuit layer [10, 20, 30 or 40], and the at least one circuit layer [10, 20, 30 or 40] has a channel width in a first direction;
at least one dielectric layer [15, 25 or 35], between the at least one circuit layer [10, 20, 30, 40]; and
Yang et al. fails to disclose
a redistribution layer, arranged above the at least one circuit layer, configured to allow at least one first solder bump and at least one second solder bump to be placed, and comprising at least one first metal contact and at least one second metal contact, wherein the at least one first solder bump and the at least one second solder bump are electrically connected to the at least one circuit layer through the at least one first metal contact and the at least one second metal contact, respectively, so that the channel width is greater than a first spacing between the at least one first solder bump and the at least one second solder bump in the first direction.
Taguchi discloses in Fig. 1
a redistribution layer, arranged above the at least one circuit layer, configured to allow at least one first solder bump and at least one second solder bump to be placed, and comprising at least one first metal contact and at least one second metal contact, wherein the at least one first solder bump and the at least one second solder bump are electrically connected to the at least one circuit layer through the at least one first metal contact and the at least one second metal contact, respectively, so that the channel width is greater than a first spacing between the at least one first solder bump and the at least one second solder bump in the first direction.
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Taguchi into the method of Yang et al. to include a redistribution layer, arranged above the at least one circuit layer, configured to allow at least one first solder bump and at least one second solder bump to be placed, and comprising at least one first metal contact and at least one second metal contact, wherein the at least one first solder bump and the at least one second solder bump are electrically connected to the at least one circuit layer through the at least one first metal contact and the at least one second metal contact, respectively, so that the channel width is greater than a first spacing between the at least one first solder bump and the at least one second solder bump in the first direction. The ordinary artisan would have been motivated to modify Yang et al. in the above manner for the purpose of providing method for forming electrical connection between the wiring substrate and the semiconductor devices.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA T NGUYEN whose telephone number is (571)272-1686. The examiner can normally be reached 9:00am -5:00 pm, Monday-Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT D HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893
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