Prosecution Insights
Last updated: August 17, 2026
Application No. 18/761,415

ELECTRONIC DEVICE INCLUDING A SEMICONDUCTOR PACKAGE AND A METHOD OF MANUFACTURING THE ELECTRONIC DEVICE

Non-Final OA §102§103
Filed
Jul 02, 2024
Priority
Sep 06, 2023 — RE 10-2023-0118311
Examiner
ISAAC, STANETTA D
Art Unit
Tech Center
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
49%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
829 granted / 968 resolved
+25.6% vs TC avg
Minimal -37% lift
Without
With
+-36.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
42 currently pending
Career history
1025
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
51.7%
+11.7% vs TC avg
§102
43.4%
+3.4% vs TC avg
§112
4.4%
-35.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 968 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This office action is in response to the application filed on 7/02/24. Claims 1-20 are pending. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) was submitted on 7/02/24. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Specification The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-5, 8-14, 17 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang et al. (US PGPub 2019/0074251, hereinafter referred to as “Kang”, IDS reference). Kang discloses the semiconductor device as claimed. See figure 1A and corresponding text, where Jang teaches, in claim 1, an electronic device, comprising: a main board (10); a semiconductor package (200) disposed on the main board (10) and mounted via a plurality of conductive connection members (12, 162); and an electromagnetic shielding member (300) covering an upper surface and side surfaces of the semiconductor package (200), wherein the plurality of conductive connection members (12, 162) includes: a plurality of signal connection balls (162) disposed on a middle region of a lower surface of the semiconductor package (200) and having a first diameter; and a plurality of electromagnetic shielding balls (164) spaced apart from each other along an edge of the lower surface of the semiconductor package (200), the electromagnetic shielding balls (164) surrounding the middle region and having a second diameter smaller than the first diameter (figure 1A; [0018-0044]). Kang teaches, in claim 2, wherein the semiconductor package includes: a package substrate having an upper surface and a lower surface and having signal substrate pads and ground substrate pads on the lower surface of the package substrate; a semiconductor chip mounted on the upper surface of the package substrate; and a sealing member covering the semiconductor chip (figure 1A; [0018-0044]). Kang teaches, in claim 3, wherein the plurality of signal connection balls are disposed on the signal substrate pads, and the plurality of electromagnetic shielding balls are disposed on the ground substrate pads (figure 1A; [0018-0044]). Kang teaches, in claim 4, wherein the package substrate includes a ground wiring, and a portion of the ground wiring is exposed from a side surface of the package substrate and is in contact with the electromagnetic shielding member (figure 1A; [0018-0044]). Kang teaches, in claim 5, wherein at least portions of the plurality of electromagnetic shielding balls to overlap the side surfaces of the semiconductor package (figure 1A; [0018-0044]). Kang teaches, in claim 8, wherein the main board includes a plurality of signal pads on which the plurality of signal connection balls are disposed, a plurality of ground pads on which the plurality of electromagnetic shielding balls are disposed, and a protective layer having openings that expose the plurality of signal pads and the plurality of ground pads, and wherein a diameter of each of the plurality of signal pads is smaller than a diameter of the opening of the protective layer, and a diameter of each of the plurality of ground pads is greater than the diameter of the opening of the protective layer (figure 1A; [0018-0044]). Kang teaches, in claim 9, wherein each of the plurality of electromagnetic shielding balls includes a core ball that includes a core and a solder layer covering the core (figure 1A; [0018-0044]). Kang teaches, in claim 10, wherein the main board includes a plurality of ground pads and solder-on pads disposed on the plurality of ground pads, and wherein the plurality of electromagnetic shielding balls are disposed on the solder-on pads (figure 1A; [0018-0044]). Kang teaches, in claim 11, an electronic device, comprising: a main board having a plurality of signal pads and a plurality of ground pads; a semiconductor package disposed on the main board, the semiconductor package including a package substrate having signal substrate pads disposed in a middle region on a lower surface of the package substrate and ground substrate pads disposed in an edge region surrounding the middle region, a semiconductor chip mounted on an upper surface of the package substrate, and a sealing member covering the semiconductor chip; an electromagnetic shielding member covering an upper surface and side surfaces of the semiconductor package; a plurality of signal connection balls disposed between the plurality of signal pads and the signal substrate pads and having a first diameter; and a plurality of electromagnetic shielding balls disposed between the plurality of ground pads and the ground substrate pads and having a second diameter smaller than the first diameter (figure 1A; [0018-0044]). Kang teaches, in claim 12, wherein the plurality of electromagnetic shielding balls are arranged in a line and spaced apart from each other along an edge of the package substrate (figure 1A; [0018-0044]). Kang teaches, in claim 13, wherein at least portions of the plurality of electromagnetic shielding balls to overlap a side surface of the package substrate (figure 1A; [0018-0044]). Kang teaches, in claim 14, wherein the package substrate includes a ground wiring therein, and a portion of the ground wiring is exposed from a side surface of the package substrate and is in contact with the electromagnetic shielding member (figure 1A; [0018-0044]). Kang teaches, in claim 17, wherein the main board includes a protective layer having openings that expose the plurality of signal pads and the plurality of ground pads, and a diameter of each of the plurality of signal pads is smaller than a diameter of the opening of the protective layer, and a diameter of each of the plurality of ground pads is greater than the diameter of the opening of the protective layer (figure 1A; [0018-0044]). Kang teaches, in claim 18, wherein each of the plurality of electromagnetic shielding balls includes a core ball that includes a core and a solder layer covering the core (figure 1A; [0018-0044]). Kang teaches, in claim 19, wherein the main board further includes solder-on pads disposed on each of the plurality of ground pads, wherein the plurality of electromagnetic shielding balls are disposed on the solder-on pads (figure 1A; [0018-0044]). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 6, 7, 15, 16 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US PGPub 2019/0074251, hereinafter referred to as “Kang”, IDS reference). Kang discloses the semiconductor device substantially as claimed see the rejection above. However, Kang fails to teach, in claim 6, wherein the first diameter is 400 μm to 500 μm, and the second diameter is 200 μm to 400 μm. Kang teaches, in claim 6, that the electromagnetic shielding terminals assist in controlling the bending of the semiconductor package ([0072]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate wherein the first diameter is 400 μm to 500 μm, and the second diameter is 200 μm to 400 μm, according to the teachings of Kang, with the motivation of preventing the semiconductor package from bending. a variable which achieves a recognized result, before the determination of the optimum or workable ranges of said variable might be characterized as routine experimentation, because "obvious to try" is not a valid rationale for an obviousness finding. In KSR International Co. v. Teleflex Inc., 550 U.S. 398 (2007), However, Kang fails to teach, in claim 7, wherein a distance between adjacent electromagnetic shielding balls is 80 μm to 150 μm. Kang teaches, in claim 7, that the electromagnetic shielding terminals assist in controlling the bending of the semiconductor package ([0072]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate wherein a distance between adjacent electromagnetic shielding balls is 80 μm to 150 μm, according to the teachings of Kang, with the motivation of preventing the semiconductor package from bending. a variable which achieves a recognized result, before the determination of the optimum or workable ranges of said variable might be characterized as routine experimentation, because "obvious to try" is not a valid rationale for an obviousness finding. In KSR International Co. v. Teleflex Inc., 550 U.S. 398 (2007), However, Kang fails to teach, in claim 15, wherein the first diameter is 400 μm to 500 μm, and the second diameter is 200 μm to 400 μm. Kang teaches, in claim 15, that the electromagnetic shielding terminals assist in controlling the bending of the semiconductor package ([0072]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate wherein the first diameter is 400 μm to 500 μm, and the second diameter is 200 μm to 400 μm, according to the teachings of Kang, with the motivation of preventing the semiconductor package from bending. a variable which achieves a recognized result, before the determination of the optimum or workable ranges of said variable might be characterized as routine experimentation, because "obvious to try" is not a valid rationale for an obviousness finding. In KSR International Co. v. Teleflex Inc., 550 U.S. 398 (2007), However, Kang fails to teach, in claim 16, wherein a distance between neighboring electromagnetic shielding balls is 80 μm to 150 μm. Kang teaches, in claim 16, that the electromagnetic shielding terminals assist in controlling the bending of the semiconductor package ([0072]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate wherein a distance between neighboring electromagnetic shielding balls is 80 μm to 150 μm, according to the teachings of Kang, with the motivation of preventing the semiconductor package from bending. a variable which achieves a recognized result, before the determination of the optimum or workable ranges of said variable might be characterized as routine experimentation, because "obvious to try" is not a valid rationale for an obviousness finding. In KSR International Co. v. Teleflex Inc., 550 U.S. 398 (2007), Kang teaches, in claim 20, an electronic device, comprising: a main board (10); a semiconductor package (200) disposed on the main board (10); an electromagnetic shielding member (300) covering an upper surface and side surfaces of the semiconductor package (200); a plurality of signal connection balls (162) disposed between the main board and the semiconductor package, disposed on a middle region of a lower surface of the semiconductor package, and having a first diameter; and a plurality of electromagnetic shielding balls (164) disposed between the main board and the semiconductor package, spaced apart from each other along an edge of the lower surface of the semiconductor package to surround the middle region, and having a second diameter smaller than the first diameter (figure 1A; [0018-0044]). However, Kang fails to teach, in claim 20, wherein the first diameter is 400 μm to 500 μm, and the second diameter is 200 μm to 400 μm, and wherein a distance between neighboring electromagnetic shielding balls is 80 μm to 150 μm. Kang teaches, in claim 20, that the electromagnetic shielding terminals assist in controlling the bending of the semiconductor package ([0072]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate wherein the first diameter is 400 μm to 500 μm, and the second diameter is 200 μm to 400 μm, and wherein a distance between neighboring electromagnetic shielding balls is 80 μm to 150 μm, according to the teachings of Kang, with the motivation of preventing the semiconductor package from bending. a variable which achieves a recognized result, before the determination of the optimum or workable ranges of said variable might be characterized as routine experimentation, because "obvious to try" is not a valid rationale for an obviousness finding. In KSR International Co. v. Teleflex Inc., 550 U.S. 398 (2007), Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STANETTA D ISAAC/Examiner, Art Unit 2898 July 11, 2026
Read full office action

Prosecution Timeline

Jul 02, 2024
Application Filed
Jul 15, 2026
Non-Final Rejection mailed — §102, §103
Aug 05, 2026
Interview Requested

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
49%
With Interview (-36.9%)
2y 5m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 968 resolved cases by this examiner. Grant probability derived from career allowance rate.

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