Prosecution Insights
Last updated: April 19, 2026
Application No. 18/761,592

AIR CURTAIN FOR DEFECT REDUCTION

Non-Final OA §102§103§DP
Filed
Jul 02, 2024
Examiner
MCCLAIN, GERALD
Art Unit
3652
Tech Center
3600 — Transportation & Electronic Commerce
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
2y 7m
To Grant
89%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allow Rate
575 granted / 773 resolved
+22.4% vs TC avg
Moderate +15% lift
Without
With
+14.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
42 currently pending
Career history
815
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
36.9%
-3.1% vs TC avg
§102
34.7%
-5.3% vs TC avg
§112
22.8%
-17.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 773 resolved cases

Office Action

§102 §103 §DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 6-9, and 12-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Suma (JP 4-92410). Claim 1: a first processing device comprising a first entryway (6 with 3; processing includes transferring a wafer); a second processing device comprising a second entryway (1 with 3); and a first air curtain device (8/9b) and a second air curtain (another 8/9b) device positioned at the first entryway and the second entryway, respectively, and between the first and second processing devices, wherein one or more of the first and second air curtain devices comprise an inner air curtain device and an outer air curtain device (9b includes 7/8/9a/etc. as shown in at least figure 2); Claim 6: wherein the first and second air curtain devices are configured to generate a substantially vertical and downward laminar flow (figure 2; “Then, a flow in a certain direction, that is, a gas curtain C is formed” denotes laminar flow); Claim 7: wherein the laminar flow comprises an inert gas comprising one or more of air, nitrogen (N2), oxygen (O2), and ozone (O3) (“oxidation” implies O2); Claim 8: wherein one or more of the first and second air curtain devices are configured to flow an inert gas, under pressure, towards an exhaust system (7 provides pressure for O2); Claim 9: performing, in a first processing device, a first semiconductor processing operation on a wafer (6 with 3; processing includes transferring a wafer); transferring, from the first processing device to a second processing device, the wafer through a first air curtain device (8/9b) and a second air curtain device (another 8/9b) disposed inside and outside of at least one of the first processing device and the second processing device (9b includes 7/8/9a/etc. as shown in at least figure 2); and performing, in the second processing device, a second semiconductor processing operation on the wafer (1 with 3); Claim 12: wherein transferring the wafer comprises exposing the wafer to a gas that is under pressure to flow into an exhaust system (7 provides pressure for O2); Claim 13: wherein transferring the wafer comprises generating, with the first and second air curtain devices, a substantially vertical and downward laminar flow (figure 2; “Then, a flow in a certain direction, that is, a gas curtain C is formed” denotes laminar flow); Claim(s) 1-4, 9-12, 15-18, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sakai et al. (2019/0096702) (“Sakai”). Claim 1: a first processing device comprising a first entryway (31 top left of FIG. 1); a second processing device comprising a second entryway (31 top right of FIG. 1); and a first air curtain device (curtain at 72 at top left of FIG. 1) and a second air curtain (curtain at 72 at top right of FIG. 1) device positioned at the first entryway and the second entryway, respectively, and between the first and second processing devices, wherein one or more of the first and second air curtain devices comprise an inner air curtain device and an outer air curtain device (one curtain at 72 is inner air curtain and other curtain at 72 is outer air curtain); Claim 2: a wafer loading station (23a); a wafer unloading station (23b); and a wafer transport system, comprising: a track connected to the wafer loading station, the wafer unloading station, and the first and second processing devices (44); and a robotic arm configured to move a wafer from the wafer loading station, into and out of the first and second processing devices, through the first and second air curtain devices, and to the wafer unloading station (40); Claim 3: an additional processing device having one or more additional entryways; and an additional air curtain device positioned at each of the one or more additional entryways to shield the wafer from contamination (other 31/72 under uppermost 31/72 in FIG. 1) Claim 4: wherein the first processing device, the second processing device, and the additional processing device are positioned along the track, and wherein the robotic arm loads and unloads the wafer into and out of the first processing device, the second processing device, and the additional processing device (FIG. 1) Claim 9: performing, in a first processing device (31 top left of FIG. 1), a first semiconductor processing operation on a wafer (transferring is a process); transferring, from the first processing device to a second processing device (31 top right of FIG. 1), the wafer through a first air curtain device (curtain at 72 at top left of FIG. 1) and a second air curtain device (curtain at 72 at top right of FIG. 1) disposed inside and outside of at least one of the first processing device and the second processing device (FIG. 1); and performing, in the second processing device, a second semiconductor processing operation on the wafer (31 top right of FIG. 1; transferring is a process); Claim 10: moving the wafer from a wafer loading station, into and out of the first and second processing devices, through the first and second air curtain devices, and to a wafer unloading station (out of 23a; into 23b); Claim 11: after performing the second semiconductor processing operation, transferring the wafer from a wafer unloading station to a container (via 22); Claim 12: wherein transferring the wafer comprises exposing the wafer to a gas that is under pressure to flow into an exhaust system (pressure at least via nozzle; arrows in FIG. 5); Claim 15: a track (44) connecting a wafer loading station and a wafer unloading station (23a/23b); a wafer processing device arranged along the track and comprising an entryway (31 top left of FIG. 1); a wafer transport system (40) configured to transport a wafer among the wafer processing device, the wafer loading station, and the wafer unloading station; and an air curtain device at the entryway of the wafer processing device, wherein the air curtain device comprises an inner air curtain device and an outer air curtain device (curtain at 72 at top left and right of FIG. 1); Claim 16: a controller device configured to synchronize an operation of the air curtain device with an operation of the entryway to which the air curtain device is attached (80; transferring is an operation); Claim 17: a controller device configured to coordinate motion of a robotic arm (41a/41b/etc.) to transfer the wafer into and out of the wafer processing device and through the air curtain device (80); Claim 18: wherein the air curtain device is configured to activate upon activation of the wafer processing device, and wherein activation of the wafer processing device comprises one or more of a power-on procedure, a door opening procedure, and a start-up procedure (turning on the device is part of power-on/start-up procedures that activates 72); Claim 20: wherein the laminar flow comprises an inert gas comprising one or more of air, nitrogen (N2), oxygen (O2), and ozone (O3) (para. [0040], N2). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 5 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakai in view of Sasaki (US 2003/0066797). Sakai discloses all the limitations of the claims as discussed above. Sakai does not directly show: Claim 5: wherein one or more of the first and second processing devices are configured to process a wafer using a solvent, and wherein the solvent is a liquid, a vapor, a gas, or an aerosol; Claim 14: wherein performing one or more of the first and second semiconductor processing operations comprise processing the wafer using a solvent, and wherein the solvent is a liquid, a vapor, a gas, or an aerosol. Sasaki shows a similar device having: Claim 5: wherein one or more of the first and second processing devices are configured to process a wafer using a solvent, and wherein the solvent is a liquid, a vapor, a gas, or an aerosol (para. [0073]); Claim 14: wherein performing one or more of the first and second semiconductor processing operations comprise processing the wafer using a solvent, and wherein the solvent is a liquid, a vapor, a gas, or an aerosol (para. [0073]); with a reasonable expectation of success for the purpose of completely drying the wafer for efficient processing of the wafer (para. [0015]-[0021]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Sakai as taught by Sasaki and include Sasaki’s similar device having: Claim 5: wherein one or more of the first and second processing devices are configured to process a wafer using a solvent, and wherein the solvent is a liquid, a vapor, a gas, or an aerosol; Claim 14: wherein performing one or more of the first and second semiconductor processing operations comprise processing the wafer using a solvent, and wherein the solvent is a liquid, a vapor, a gas, or an aerosol; with a reasonable expectation of success for the purpose of completely drying the wafer for efficient processing of the wafer. Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakai in view of Suma. Sakai discloses all the limitations of the claims as discussed above. Sakai does not directly show: Claim 19: wherein the air curtain device is configured to generate a substantially vertical and downward laminar flow. Sasaki shows a similar device having: Claim 19: wherein the air curtain device is configured to generate a substantially vertical and downward laminar flow (figure 2 shows downward laminar, straight-line flow at 13); with a reasonable expectation of success for the purpose of minimizing impurities other than high-purity gas used in a reaction chamber from entering the reaction chamber (para. [0001]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Sakai as taught by Sasaki and include Sasaki’s similar device having: Claim 19: wherein the air curtain device is configured to generate a substantially vertical and downward laminar flow; with a reasonable expectation of success for the purpose of minimizing impurities other than high-purity gas used in a reaction chamber from entering the reaction chamber. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-5, 7, 9, 12-14, and 16-20 of U.S. Patent No. 12,062,562 (“USPN”). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the current application fit into (are broader than) the above claims of USPN. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. JP 11204396 A discloses air curtains ek1/ek2 in figure 2. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Gerald McClain whose telephone number is (571)272-7803. The examiner can normally be reached Monday through Friday from 8:30 a.m. to 5:00 p.m. and at gerald.mcclain@uspto.gov (see MPEP 502.03 (II)). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Saul Rodriguez can be reached at (571) 272-7097. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Gerald McClain/Primary Examiner, Art Unit 3652
Read full office action

Prosecution Timeline

Jul 02, 2024
Application Filed
Mar 19, 2026
Examiner Interview (Telephonic)
Mar 23, 2026
Non-Final Rejection — §102, §103, §DP (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
89%
With Interview (+14.8%)
2y 7m
Median Time to Grant
Low
PTA Risk
Based on 773 resolved cases by this examiner. Grant probability derived from career allow rate.

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