DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7, 9 and 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hu et al [US 2021/0043741] IDS.
With respect to claim 1, Hu et al (figs. 4-7, cols. 3-4) disclose a semiconductor device, comprising:
a semiconductor layer (430, 435; pp [0037]);
a gate trench formed in the semiconductor layer, the gate trench extending in a first direction in plan view and having a width in a second direction orthogonal to the first direction in plan view;
an insulation layer (455; pp [0039]) formed on the semiconductor layer;
a field plate electrode (420; pp [0039]) arranged in the gate trench and having a width in the second direction; and
a gate electrode (410; pp [0038]) arranged in the gate trench and separated from the field plate electrode by the insulation layer (455; pp [0039]), wherein:
the gate trench includes a first region in which the gate electrode is located above the field plate electrode in a depth-wise direction of the gate trench, and
a second region including an end of the gate trench in the first direction; and
the field plate electrode (420; pp [0039]; fig. 7) in the second region includes a widened portion having a width that is greater than a width of the field plate electrode (420a) in the first region.
With respect to claim 2, Hu et al (figs. 4-7, cols. 3-4) disclose wherein: the widened portion is arranged at least at a specific depth position in the gate trench; and at the specific depth position, the width of the widened portion is greater than the width of the field plate electrode (420a) in the first region.
With respect to claim 3, Hu et al (figs. 4-7, cols. 3-4) disclose wherein the specific depth position is a position in the depth-wise direction at which the field plate electrode (420a) in the first region has a largest width.
With respect to claim 4, Hu et al (figs. 4-7, cols. 3-4) disclose wherein the specific depth position is a central position of the gate trench in the depth-wise direction.
With respect to claim 7, Hu et al (figs. 4-7, cols. 3-4) disclose wherein the gate trench in the second region includes a portion that accommodates at least the widened portion, the portion having a width that is greater than a width of the gate trench in the first region.
With respect to claim 9, Hu et al (figs. 4-7, cols. 3-4) disclose wherein: the field plate electrode (420; pp [0039]; fig. 7) in the second region includes a first part corresponding to the widened portion, and a second part having a smaller width than the first part; and the second part is located between the first part and the gate electrode (52) in plan view.
With respect to claim 14, Hu et al (figs. 4-7, cols. 3-4) disclose wherein the field plate electrode (420; pp [0039]; fig. 7) in the second region includes an upper surface that is located above a bottom surface of the gate electrode (410; pp [0038]) in the first region in the depth-wise direction.
With respect to claim 15, Hu et al (figs. 4-7, cols. 3-4) disclose further comprising: a gate interconnection (465, 490, pp [0043]) formed on the insulation layer; and a source interconnection (480, 495, pp [0043]) formed on the insulation layer and separated from the gate interconnection, wherein: the gate electrode is connected to the gate interconnection in the first region; and the field plate electrode is connected to the source interconnection in the second region.
Claims 1-4, 7, 9-11 and 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Qiao et al [US 10,720,524] IDS.
With respect to claim 1, Qiao et al (fig. 3A-3B, cols. 5-6) disclose a semiconductor device, comprising:
a semiconductor layer (108, 140; col. 5, lines 50-51);
a gate trench (104, 115; col. 5, lines 42-44) formed in the semiconductor layer, the gate trench extending in a first direction in plan view and having a width in a second direction orthogonal to the first direction in plan view;
an insulation layer (107, 109, 111; col. 5, lines 59-67; col. 6, lines 1-4) formed on the semiconductor layer;
a field plate electrode (106; col. 5, lines 50-67) arranged in the gate trench and having a width in the second direction; and
a gate electrode (105; col. 5, lines 50-67) arranged in the gate trench and separated from the field plate electrode by the insulation layer, wherein:
the gate trench includes a first region in which the gate electrode is located above the field plate electrode in a depth-wise direction of the gate trench, and
a second region including an end of the gate trench in the first direction; and
the field plate electrode in the second region includes a widened portion having a width that is greater than a width of the field plate electrode in the first region.
With respect to claim 2, Qiao et al (fig. 3A-3B, cols. 5-6) disclose wherein: the widened portion is arranged at least at a specific depth position in the gate trench; and at the specific depth position, the width of the widened portion is greater than the width of the field plate electrode (106) in the first region.
With respect to claim 3, Qiao et al (fig. 3A-3B, cols. 5-6) disclose wherein the specific depth position is a position in the depth-wise direction at which the field plate electrode (106) in the first region has a largest width.
With respect to claim 4, Qiao et al (fig. 3A-3B, cols. 5-6) disclose wherein the specific depth position is a central position of the gate trench in the depth-wise direction.
With respect to claim 7, Qiao et al (fig. 3A-3B, cols. 5-6) disclose wherein the gate trench in the second region includes a portion that accommodates at least the widened portion, the portion having a width that is greater than a width of the gate trench in the first region.
With respect to claim 9, Qiao et al (fig. 3A-3B, cols. 5-6) disclose wherein: the field plate electrode (106; col. 5, lines 50-67) in the second region includes a first part corresponding to the widened portion, and a second part having a smaller width than the first part; and the second part is located between the first part and the gate electrode (105; col. 5, lines 50-67) in plan view.
With respect to claim 10, Qiao et al (fig. 3A-3B, cols. 5-6) disclose wherein the width of the second part is equal to the width of the field plate electrode (106; col. 5, lines 50-67) in the first region.
With respect to claim 11, Qiao et al (fig. 3A-3B, cols. 5-6) disclose wherein the gate trench (104, 115; col. 5, lines 42-44) in the second region includes a portion that accommodates the second part, the portion having a width that is equal to a width of the gate trench in the first region.
With respect to claim 14, Qiao et al (fig. 3A-3B, cols. 5-6) disclose wherein the field plate electrode (106; col. 5, lines 50-67) in the second region includes an upper surface that is located above a bottom surface of the gate electrode (105; col. 5, lines 50-67) in the first region in the depth-wise direction.
With respect to claim 15, Qiao et al (fig. 3A-3B, cols. 5-6) disclose further comprising: a gate interconnection (131; col. 9, lines 25-307) formed on the insulation layer; and a source interconnection (130; col. 9, lines 25-307) formed on the insulation layer and separated from the gate interconnection, wherein: the gate electrode is connected to the gate interconnection in the first region; and the field plate electrode is connected to the source interconnection in the second region.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6, 8, and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al [US 2021/0043741] IDS or Qiao et al [US 10,720,524] IDS.
Hu et al or Qiao et al do not mention a thickness, a length, a width as claimed in claims 5-6, 8, and 12-13. However, the thickness, the length, the width range would have been obvious to an ordinary artisan practicing the invention because, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 233, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed dimensions of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI V PHAM whose telephone number is (571)272-1715. The examiner can normally be reached M-F 8:30a.m-10:00p.m.
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/HOAI V PHAM/Primary Examiner, Art Unit 2892
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