DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tailliet, US Patent Application Publication 2018/0033487 in view of Takasu et al, US Patent 5,982,002
Regarding claim 1, Tailliet teaches an electrically erasable and programmable nonvolatile memory device comprising a memory cell, the memory cell comprising:
a source region (S) disposed in a semiconductor body PSUB;
a drain region (D) disposed in the semiconductor body;
a channel region RCN disposed in the semiconductor body;
a control gate CG1;
a floating gate FG disposed between the semiconductor body and the control gate, wherein
the floating gate includes a protruding portion PRT that is located over the channel region between the source and drain regions and spaced therefrom, the protruding portion being separated from the channel region by a first region of an insulating layer OXTN that is thinner than a second region of the insulating layer OXHV that separates one or more remaining portions of the floating gate from the channel region; and
a counter-doped implant INJT positioned in the channel region under the first region of the insulating layer (figure 3).
Tailliet fails to teach the implant is either less P-doped than the channel region or N-doped lightly enough that the implant inverts to P-doped when a voltage is applied during an erase operation.
However, Takasu teaches an N-type doping is performed in the p-type channel region 206 under the gate insulation layer 205 in figure 12(d), in which the channel region is doped additionally by an n-type dopant such that the effective concentration level of the p-type dopant is reduced in the channel region. By doping the channel region as such, one can compensate for the increase of the threshold voltage of the channel region that is caused as a result of the increased impurity concentration level of the internal device region (See column 10, lines 43-52).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Takasu with that of Tailliet because N dopant performed in the p-type channel region can compensate for the increase of the threshold voltage of the channel region that is caused as a result of the increased impurity concentration level of the internal device region, thereby improving the device.
Taillet and Takasu fail to teach N-doped lightly enough that the implant inverts to P-doped when a voltage is applied during an erase operation.
However, in reference to this functional limitation, MPEP 2112.01 stated that when the structure recited is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. Therefore, these limitations are held to be a matter of obviousness. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). “When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product. In re Best.
Regarding claim 2, Talliet teaches the implant is positioned only under the first
region of the insulating layer and does not extend under the second region of the insulating layer (figure 3).
Regarding claim 3, Takasu teaches the implant is counter-doped with arsenic or phosphorous (column 11, lines 37-39)
Regarding claim 4, Talliet teaches an electrically erasable and programmable nonvolatile memory device comprising a memory cell, the memory cell comprising:
a source region (S) disposed in a semiconductor body (P-sub);
a drain region (D) disposed in the semiconductor body;
a channel region RCN disposed in the semiconductor body;
a control gate CG1;
a floating gate FG disposed between the semiconductor body and the control gate, wherein the floating gate includes a protruding portion PRT that is located over the channel region between the source and drain regions and spaced therefrom, the protruding portion being separated from the channel region by a first region of an insulating layer OXTN that is thinner than a second region of the insulating layer OXHV that separates one or more remaining portions of the floating gate from the channel region; and
a counter-doped implant INTJ positioned in the channel region under the first region of the insulating layer,
Talliet fails to teach the implant causes a reduction in a threshold voltage of a portion of the channel region beneath the implant.
However, Takasu teaches the N-type implant is performed in the p-type channel region 206 under the gate insulation layer 205 in figure 12(d), in which the channel region is doped additionally by an n-type dopant such that the effective concentration level of the p-type dopant is reduced in the channel region. By doping the channel region as such, one can compensate for the increase of the threshold voltage of the channel region that is caused as a result of the increased impurity concentration level of the internal device region (See column 10, lines 43-52).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Takasu with that of Tailliet because N dopant performed in the p-type channel region can compensate for the increase of the threshold voltage of the channel region that is caused as a result of the increased impurity concentration level of the internal device region, thereby improving the device.
Regarding claim 5, while Takasu teaches the implant is either less P-doped than the channel region or N-doped, Talliet and Takasu fail to teach N doped lightly enough that the implant inverts to P-doped when a voltage is applied during an erase operation.
However, in reference to this functional limitation, MPEP 2112.01 stated that when the structure recited is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. Therefore, these limitations are held to be a matter of obviousness. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). “When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product. In re Best.
Regarding claim 6, Talliet teaches the implant is positioned only under the first
region of the insulating layer and does not extend under the second region of the insulating layer (figure 3).
Regarding claim 7, Takasu teaches the implant is counter-doped with arsenic or phosphorous (column 11, lines 37-39)
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tailliet, US Patent Application Publication 2018/0033487 in view of Sawazaki, US Patent 4,217,149.
Regarding claim 8, Tailliet teaches a method of manufacturing an electrically erasable and programmable nonvolatile memory device comprising a memory cell, the method comprising:
forming a first dielectric layer OXHV over a surface of a semiconductor substrate PSUB, the first dielectric layer having a first thickness;
forming a second dielectric layer OXTN, the second dielectric layer having a second thickness less than the first thickness;
accelerating a plurality of ions toward the second dielectric layer at an energy level selected such that some of the plurality of ions penetrate the second dielectric layer in an area of the opening to form a counter-doped implant INJT in the semiconductor substrate aligned with the opening;
forming a floating gate layer FG over the second dielectric layer;
forming a control gate dielectric layer ONO over the floating gate layer;
forming a control gate layer CG1 over the control gate dielectric layer; and
removing portions of the floating gate layer, the control gate dielectric layer, and the control gate layer to form a floating gate and a control gate (as shown in figure 3).
Talliet fails to teach removing a portion of the first dielectric layer to form an opening and forming a second dielectric layer over the first dielectric layer and the opening.
However, Sawazaki teaches a generally-known means to form a thinner dielectric within a thicker dielectric material, which includes removing a portion of the first dielectric layer to form an opening and forming a second dielectric layer over the first dielectric layer and the opening (see column 4, lines 36-46) before ion implantation of a dopant into the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sawazaki with that of Taaliet because removing a portion of the first dielectric layer to form an opening and forming a second dielectric layer over the first dielectric layer and the opening is a generally-known means of forming a thinner gate oxide shown in the embodiment of Talliet.
Claim(s) 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Talliet and Sawazaki as applied to claim 8 above, and further in view of Takasu et al, US Patent 5,982,002.
Regarding claims 9-11, Talliet and Sawazaki fail to teach the plurality of ions comprises a plurality of arsenic ions or a plurality of phosphorous ions and the implant is counter-doped to a level sufficient to cause a reduction in a threshold voltage of a portion of a channel region beneath the implant, wherein the implant is either less P-doped than the semiconductor substrate or N-doped lightly enough that the implant inverts to P-doped when a voltage is applied during an erase operation.
However, Takasu teaches an N-type doping is performed (arsenic ions or a plurality of phosphorous ions, column 11, lines 37-39) in the p-type channel region 206 under the gate insulation layer 205 in figure 12(d), in which the channel region is doped additionally by an n-type dopant such that the effective concentration level of the p-type dopant is reduced in the channel region. By doping the channel region as such, one can compensate for the increase of the threshold voltage of the channel region that is caused as a result of the increased impurity concentration level of the internal device region (See column 10, lines 43-52).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Takasu with that of Tailliet and Sawazaki because N dopant performed in the p-type channel region can compensate for the increase of the threshold voltage of the channel region that is caused as a result of the increased impurity concentration level of the internal device region, thereby improving the device.
Taillet, Sawazaki, and Takasu fail to teach N-doped lightly enough that the implant inverts to P-doped when a voltage is applied during an erase operation.
However, in reference to this functional limitation, MPEP 2112.01 stated that when the structure recited is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. Therefore, these limitations are held to be a matter of obviousness. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). “When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product. In re Best.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUOVAUNDA JEFFERSON whose telephone number is (571)272-5051. The examiner can normally be reached M-F 7AM-4PM.
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/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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