DETAILED ACTION
This application, 18/761,822, attorney docket AD9667-US, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The applicant or assignee is Chengdu BOE Optoelectronics Technology Co., Ltd.., and is a Continuation of 17430229, filed 08/11/2021, now U.S. Patent # 12082460, which is a National Stage entry of PCT/CN2020/076951, International Filing Date 02/27/2020. Claims 1-20 are pending and are considered below. Note that examiner will use numbers in parentheses to indicate numbered elements in prior art figures, and brackets to point to paragraph numbers where quoted material or specific teachings can be found.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-13 19 and 20 are rejected under 35 U.S.C. 102a1/a2 as being anticipated by Lim (U.S. 2019/0181213).
As for claim 1,
Lim teaches in figures 1-3 a display substrate, comprising:
a display region (AA) and a peripheral region (NA) at least partially surrounding the display region, wherein the display region comprises an opening (at NTA) a first display region (AA21) and a second display region (AA22),
the first display region and the second region are located at opposite sides of the opening,
the first display region, the opening and the second display region are sequentially arranged along a first direction (across the page of figure 1 through the notch area), and
the peripheral region comprises an opening peripheral region at least partially located in the opening (shown between pixels in the notch area and including VDDAA, VSSA and NTA and an outer perimeter without pixels);
the display substrate further comprises a first wire and a second wire (CML in figure 2 extending from each GL), and the first wire and the second wire are configured to transmit electrical signals for the display region (connect gate signals [0041]);
the first wire and the second wire pass through the first display region, the opening peripheral region and the second display region, sequentially (shown in figure 2);
in the opening peripheral region, the first wire comprises a first bent portion, and the second wire comprises a second bent portion.
As for claim 3,
Lim teaches the display substrate according to claim 1, wherein the first bent portion of the first wire and the second bent portion of the second wire are centrally symmetrical about a center between the first bent portion and the second bent portion. (shown in figure 2).
As for claim 4,
Lim teaches the display substrate according to claim 1, wherein the first wire and the second wire are arranged on a same layer. (all are in the CML layer in figure 5A)
As for claim 5,
Lim teaches the display substrate according to claim 1, wherein the first bent portion and the second bent portion are arranged side by side along the first direction (a horizontal line crosses multiple wires).
As for claim 6,
Lim teaches the display substrate according to claim 1, wherein the first display region and the second display region comprise a plurality of rows of sub-pixels (P) separated by the opening (shown in figure 1),
the first wire is configured to provide a scan signal for a first row of sub-pixels arranged in the first direction in the first display region and the second display region, and
the second wire is configured to provide a scan signal for a second row of sub-pixels arranged in the first direction in the first display region and the second display region. (all CML wires are connected to the gate wires to equalize the scan load [[0064]).
As for claim 7.
The display substrate according to claim 6, and teaches in figure 5B, the opening peripheral region comprises a semiconductor pattern (act) and a conductive pattern (PL);
the semiconductor pattern is located on a base substrate (SUB),
the first wire and the second wire (CML) are located on a side of the semiconductor pattern away from the base substrate, and
the conductive pattern is located on a side of the first wire and the second wire away from the semiconductor pattern; and
in a direction perpendicular to the base substrate, the first wire is spaced apart and insulated from at least one of the semiconductor pattern and the conductive pattern to be capable of forming a capacitor (C2), and
the second wire is spaced apart and insulated from at least one of the semiconductor pattern and the conductive pattern to be capable of forming a capacitor (C1).
As for claim 8,
Lim teaches the display substrate according to claim 7, wherein in the direction perpendicular to the base substrate,
the first bent portion of the first wire is spaced apart and insulated from at least one of the semiconductor pattern and the conductive pattern to be capable of forming a capacitor, and
the second bent portion of the second wire is spaced apart and insulated from at least one of the semiconductor pattern and the conductive pattern to be capable of forming a capacitor. (because the layers continue around the opening, the bend portions will be arranged as 5a or 5b).
As for claim 9,
Lim teaches the display substrate according to claim 7, and Lim teaches a third wire, which is arranged on a same layer as the first wire and the second wire, wherein the third wire passes through the first display region, the opening peripheral region and the second display region, sequentially, and
the third wire extends along the first direction, and is configured to provide a scan signal for a third row of pixels arranged along the first direction in the first display region and the second display region, and
the third wire is spaced apart and insulated from at least one of the semiconductor pattern and the conductive pattern to be capable of forming a capacitor. (Lim shows 8 wires that will be arranges in the same layers and act as scan line extensions).
As for claim 10.
Lim teaches the display substrate according to claim 9, and Lim teaches that a count of sub-pixels comprised in the third row of sub-pixels is greater than a count of sub-pixels comprised in the first row of sub-pixels; or
the count of sub-pixels comprised in the third row of sub-pixels is greater than a count of sub-pixels comprised in the second row of sub-pixels; or
the count of sub-pixels comprised in the third row of sub-pixels is greater than the count of sub-pixels comprised in the first row of sub-pixels, and greater than the count of sub-pixels comprised in the second row of sub-pixels. (in figure 2, the top 3 rows shown have a greater number of pixels.)
As for claim 11,
Lim teaches the display substrate according to claim 9, wherein the display region further comprises
a third display region, (AA1) and two opposite edges, extending along a second direction perpendicular to the first direction (up the figure), of the third display region, are
respectively aligned with an edge, extending along the second direction and away from the opening, of the first display region and an edge, extending along the second direction and away from the opening, of the second display region (outer edges are continuous along the direction up the figure); and
the third display region comprises a plurality of sub-pixels arranged in multiple rows and multiple columns, (partially shown in figure 2) and
further comprises a plurality of fourth wires (GL) extending along the first direction, and each of the plurality of fourth wires is configured to provide a scan signal for each row of sub-pixels among the multiple rows and multiple columns of sub-pixels.
As for claim 12,
Lim teaches the display substrate according to claim 11, and Lim teaches a count of sub-pixels comprised in each row of sub-pixels among the multiple rows and multiple columns of sub-pixels is greater than a count of sub-pixels comprised in the first row of sub-pixels, greater than a count of sub-pixels comprised in the second row of sub-pixels, and greater than a count of sub-pixels comprised in the third row of sub-pixels. (shown in figure 2).
As for claim 13,
Lim teaches the display substrate according to claim 7 and teaches that the semiconductor pattern comprises a plurality of semiconductor lines (gate lines into the page) extending along a second direction, the second direction is perpendicular to the first direction, and the conductive pattern is continuously arranged on a side of the first wire and the second wire away from the semiconductor pattern (fig.5B).
As for claim 14,
Lim teaches the display substrate according to claim 7, and Lim teaches comprising:
a first insulating layer (GI) and a second insulating layer (ILS1), wherein the first insulating layer is located on a side of the semiconductor pattern away from the base substrate, the first wire and the second wire are located on a side of the first insulating layer away from the semiconductor pattern;
the second insulating layer is located on a side of the first wire and the second wire away from the first insulating layer;
a via hole is provided in the first insulating layer and the second insulating layer, and the semiconductor pattern and the conductive pattern are electrically connected through the via hole in the first insulating layer and the second insulating layer. (shown as DE and SE).
As for claim 19,
Lim teaches in figures 1-3, and 5a and 5b, a display apparatus, comprising a display substrate (SUB),
wherein the display substrate comprises a display region (AA) and a peripheral region (NA) at least partially surrounding the display region, wherein the display region comprises an opening (sat NTA), a first display region (AA21) and a second display region (AA22), the first display region and the second region are located at opposite sides of the opening,
the first display region, the opening and the second display region are sequentially arranged along a first direction (shown in fig. 2), and the peripheral region comprises an opening peripheral region at least partially located in the opening (shown between pixels in the notch area and including VDDAA, VSSA and NTA and an outer perimeter without pixels);
the display substrate further comprises a first wire and a second wire CML in figure 2 extending from each GL) and the first wire and the second wire are configured to transmit electrical signals for the display region (connect gate signals [0041]);
the first wire and the second wire pass through the first display region, the opening peripheral region and the second display region, sequentially (fig. 2);
in the opening peripheral region, the first wire comprises a first bent portion, the second wire comprises a second bent portion (each has 4 bends around NTA).
As for claim 20,
Lim teaches the display apparatus according to claim 19, wherein the opening peripheral region comprises a semiconductor pattern (ACT) and a conductive pattern (CML); and in a direction perpendicular to the base substrate, at least one of the first wire and the second wire is spaced apart and insulated from one of the semiconductor pattern and the conductive pattern to form a capacitor. (shown as C2 in figure 5B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability should not be negated by the manner in which the invention was made.
Claims 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Lim in view of Ka et al. (U.S. 2017/0301280).
As for claim 15,
Lim teaches the display substrate according to claim 7, wherein the display region comprises a plurality of sub-pixels, and each of the plurality of sub-pixels comprises a pixel circuit, the pixel circuit comprises a thin film transistor which has an active layer (ACT), a gate electrode (GE) and source-drain electrodes (SE/DE).
But Lim does not teach that the pixel comprises a storage capacitor, which comprises a first capacitor plate and a second capacitor plate;
and the gate electrode is arranged on a same layer as the first capacitor plate, and the first wire and the second wire are arranged on a same layer as the second capacitor plate.
However, Ka teaches in figures 9 and 10 storage capacitor, which comprises a first capacitor plate (LE) and a second capacitor plate (UE);
and the gate electrode (GE7) is arranged on a same layer as the first capacitor plate (On GI), and the first wire and the second wire are arranged on a same layer as the second capacitor plate (Es/EE, the connection wires of Ka are on IL1 in figure 14, UE is on IL1 in figure 9).
It would have been obvious to one skilled in the art at the effective filing date of this application arrange the wire layer as taught by KA because it minimizes the number of metal layers, and use a capacitor in the pixel circuit as taught by Ka because the capacitor allows the pixel to continuously emit light during the frame period. Sonehara [0108]. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 16.
Lim in view of Ka makes obvious the display substrate according to claim 15, and in the combination, Lim teaches that the semiconductor pattern is arranged on a same layer as the active layer, and the conductive pattern is arranged on a same layer as the source-drain electrodes. (fig. 3).
As for claim 17,
Lim in view of Ka makes obvious the display substrate according to claim 15, and Lim teaches the opening peripheral region further comprises
a power line pattern (Vssa) electrically connected to the conductive pattern ([0045]),
the power line pattern is configured to provide an electrical signal for the conductive pattern (from HP power link), and
the display region further comprises a first power line (vddl) electrically connected to the pixel circuit, and the power line pattern and the first power line are arranged on a same layer.
As for claim 18,
Lim in view of Ka makes obvious the display substrate according to claim 15, wherein the opening peripheral region further comprises
a power line pattern (Vddl) electrically connected to the conductive pattern, the power line pattern is configured to provide an electrical signal for the conductive pattern, ([0045]
each of the plurality of sub-pixels further comprises a light emitting element (oled), the light emitting element comprises a cathode (E1), an anode (E2), and a light emitting layer (EML) between the cathode and the anode, and one of the cathode and the anode is electrically connected to the pixels circuit (through DE), but does not teach that the power line pattern and the anode are arranged on a same layer.
However, selecting an available layer to deposit a wiring line is a rearrangement of parts, and is considered to be an obvious modification of the device
. It would have been obvious to one having ordinary skill in the art at the time of the invention that was made to rearrange the locations of the power line pattern with no change in the device’s function, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As for claim 2,
The prior art does not teach or make obvious at least one of the first bent portion and the second bent portion of the wires that cross the opening peripheral region comprises at least one S-shaped bent portion.
Conclusion
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/JOHN A BODNAR/Primary Examiner, Art Unit 2893
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