DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/02/2024 and 11/01/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 8-18 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US PG Pub 2024/0429281 to Chen et al (hereinafter Chen).
Regarding Claim 8, Chen discloses a semiconductor device, comprising:
a substrate (50, Fig. 1) including a first active region and a second active region that are adjacent to each other;
a first active pattern (62) on the first active region and a second active pattern (62) on the second active region;
a first channel pattern (68, Fig. 14) on the first active pattern and a second channel pattern (68) on the second active pattern;
a first gate electrode (128, Fig. 13B) on the first channel pattern and a second gate electrode (128) on the second channel pattern;
a first gate dielectric layer (112A, Fig. 14) between the first channel pattern and the first gate electrode; and
a second gate dielectric layer (112A) between the second channel pattern and the second gate electrode,
wherein each of the first and second gate dielectric layers includes a first high-k dielectric layer (112B-1) and a second high-k dielectric layer (112B-2),
wherein the first high-k dielectric layer of the first gate dielectric layer includes a first dipole element [0063], and
wherein the first high-k dielectric layer of the second gate dielectric layer includes a second dipole element [0063].
Regarding Claim 9, Chen discloses the semiconductor device of Claim 8, wherein each of the first and second channel patterns includes first, second, and third semiconductor patterns that are stacked to be spaced apart from each other (Fig. 13B).
Regarding Claim 10, Chen discloses the semiconductor device of Claim 8, wherein
the first gate electrode includes a first metal pattern (122, Fig. 22) and a fill metal pattern (126) on the first channel pattern,
the second gate electrode includes a capping pattern (124), a second metal pattern (118), and the fill metal pattern (126) on the second channel pattern, and
the first metal pattern and the second metal pattern have different work functions from each other [0070] & [0079].
Regarding Claim 11, Chen discloses the semiconductor device of Claim 8, wherein the first dipole element and the second dipole element are different from each other [0070] & [0079].
Regarding Claim 12, Chen discloses the semiconductor device of Claim 8, wherein
the first dipole element increases an effective work function of the first gate electrode [0070], and
the second dipole element decreases an effective work function of the second gate electrode [0079].
Regarding Claim 13, Chen discloses the semiconductor device of Claim 8, wherein the first high-k dielectric layer and the second high-k dielectric layer include a same high-k dielectric material [0070] & [0079].
Regarding Claim 14, Chen discloses the semiconductor device of Claim 8, wherein
the first gate dielectric layer includes a first dipole layer between the first high-k dielectric layer and the second high-k dielectric layer (Fig. 14), and
the second gate dielectric layer includes a second dipole layer between the first high-k dielectric layer and the second high-k dielectric layer (Fig. 14).
Regarding Claim 15, Chen discloses the semiconductor device of Claim 14, wherein each of the first and second dipole layers is provided in plural (Fig. 14).
Regarding Claim 16, Chen discloses a semiconductor device, comprising:
a substrate (50, Fig. 1) including a first region and a second region that are spaced apart from each other;
a logic cell on the first region and including a logic transistor (the function of the transistor does not give much patentable weight for the structure); and
a memory cell on the second region and including a memory transistor (the function of the transistor does not give much patentable weight for the structure),
wherein the logic transistor includes
a first channel pattern (68, Fig. 14),
a first gate electrode (128, Fig. 13B) on the first channel pattern, and
a first gate dielectric layer (112) between the first channel pattern and the first gate electrode,
wherein the memory transistor includes,
a second channel pattern (68),
a second gate electrode (128) on the second channel pattern, and
a second gate dielectric layer (112) between the second channel pattern and the second gate electrode,
wherein each of the first and second gate dielectric layers includes a first high-k dielectric layer (112B-1) and a second high-k dielectric layer (112B-2), and
wherein the first gate dielectric layer further includes a first dipole layer between the first high-k dielectric layer and the second high-k dielectric layer [0063].
Regarding Claim 17, Chen discloses the semiconductor device of Claim 16, wherein
the first dipole layer includes a first dipole element that adjusts an effective work function of the first gate electrode [0063], and
the first high-k dielectric layer of the first gate dielectric layer includes the first dipole element [0063].
Regarding Claim 18, Chen discloses the semiconductor device of Claim 17, wherein the second gate dielectric layer further includes a second dipole layer between the first high-k dielectric layer and the second high-k dielectric layer (Fig. 14),
wherein the second dipole layer of the second gate dielectric layer includes a second dipole element different from the first dipole element (Fig. 14), and
wherein the first high-k dielectric layer of the second gate dielectric layer includes the second dipole element [0063].
Regarding Claim 20, Chen discloses the semiconductor device of Claim 16, wherein
the memory cell is a static random access memory (SRAM) cell (the function of the transistor does not give much patentable weight for the structure), and
the memory transistor is one of a pull-down transistor or a pull-up transistor (the function of the transistor does not give much patentable weight for the structure).
Allowable Subject Matter
Claims 1-7 are allowed.
Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 1 recites a semiconductor device, comprising:
an active pattern on an active region of a substrate;
a channel pattern on the active pattern, the channel pattern including first, second, and third semiconductor patterns that are stacked to be spaced apart from each other;
a gate electrode on the channel pattern; and
a gate dielectric layer between the channel pattern and the gate electrode,
wherein the gate dielectric layer includes
an interface layer, and
first, second, and third high-k dielectric layers that are sequentially stacked on the interface layer,
wherein the first high-k dielectric layer includes a first dipole element, and
wherein the second high-k dielectric layer includes a second dipole element.
The following is a statement of reasons for the indication of allowable subject matter:
Chen discloses the use of two high-k dielectric layers including first and second dipole materials but does not disclose a third high-k dielectric layer over the first and second dipole containing high-k layers. It is not apparent that Chen’s device would benefit from or function equally as well if a third high-k dielectric layer were included. Claim 19 recites similar subject matter to that of Claim 1 and would be allowable if included in Claim 16. Claims 2-7 depend on Claim 1 and are allowable for at least the reasons above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID C SPALLA whose telephone number is (303)297-4298. The examiner can normally be reached Mon-Fri 10am-5pm MST.
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/DAVID C SPALLA/ Primary Examiner, Art Unit 2893
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