DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This OA is in response to the claims filled on 7/2/2024 that has been entered, wherein claims 1-20 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/2/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation "the seed metal layer" in line 9. There is insufficient antecedent basis for this limitation in the claim. Is the seed metal layer of line 9 the same or different than a seed metal layer pattern of line 5. For the purpose of examination, “the seed metal layer” will be interpreted as “seed metal layer pattern”.
Claims 11-16 depend on claim 10 and inherit it deficiencies.
Claim 17 recites the limitation of “the uppermost surface of the seed metal layer pattern being exposed by the seed metal layer pattern” in line 15. How can the seed metal layer pattern expose itself? For the purpose of examination, ““the uppermost surface of the seed metal layer pattern being exposed by the seed metal layer pattern” will be interpreted as ““the upper sidewall of the first metal pattern being exposed by the seed metal layer pattern”.
Claims 18-20 depend on claim 17 and inherit it deficiencies.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 4-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Miller et al. (US 5,714,804).
Regarding claim 1, Miller teaches an interconnection structure in a semiconductor device(Fig. 4I), comprising:
a substrate(14);
a first insulating interlayer(8, col. 5, lines 21-61) on the substrate(14);
a first metal pattern(20, col. 5, lines 21-61) on the substrate(14) and passing through the first insulating interlayer(8, col. 5, lines 21-61);
a seed metal layer pattern(Ti layer of 2, col. 5, lines 21-61, col. 1, lines 36-64) surrounding a portion of a sidewall of the first metal pattern(20, col. 5, lines 21-61), a bottom of the first metal pattern(20, col. 5, lines 21-61), an upper sidewall of the first metal pattern(20, col. 5, lines 21-61) and an upper surface of the first metal pattern(20, col. 5, lines 21-61), the upper sidewall of the first metal pattern(20, col. 5, lines 21-61) and the upper surface of the first metal pattern(20, col. 5, lines 21-61) being exposed by the seed metal layer pattern(Ti layer of 2, col. 5, lines 21-61, col. 1, lines 36-64); and
a second metal pattern(22, col. 6, lines 5-30) directly contacting an uppermost surface of the seed metal layer pattern(Ti layer of 2, col. 5, lines 21-61, col. 1, lines 36-64), the upper sidewall of the first metal pattern(20, col. 5, lines 21-61), and the upper surface of the first metal pattern(20, col. 5, lines 21-61), the second metal pattern(22, col. 6, lines 5-30) filling at least a recess between the first insulating interlayer(8, col. 5, lines 21-61) and the first metal pattern(20, col. 5, lines 21-61).
Regarding claim 2, Miller teaches the interconnection structure in the semiconductor device of claim 1, wherein a resistance(resistance of aluminum, col. 5, lines 21-61) of the first metal pattern(20, col. 5, lines 21-61) is lower than a resistance(resistance of titanium, col. 5, lines 21-61) of the seed metal layer pattern(Ti layer of 2, col. 5, lines 21-61, col. 1, lines 36-64).
Regarding claim 4, Miller teaches the interconnection structure in the semiconductor device of claim 1, further comprising:
a barrier pattern(TiN layer of 2, col. 5, lines 21-61, col. 1, lines 36-64) between a bottom of the seed metal layer pattern(Ti layer of 2, col. 5, lines 21-61, col. 1, lines 36-64) and a surface of the substrate(14).
Regarding claim 5, Miller teaches the interconnection structure in the semiconductor device of claim 4, wherein the barrier pattern(TiN layer of 2, col. 5, lines 21-61, col. 1, lines 36-64) surrounds an outer surface of the seed metal layer pattern(Ti layer of 2, col. 5, lines 21-61, col. 1, lines 36-64).
Claims 1-2 and 4-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chung et al. (US 2023/0215930 A1).
Regarding claim 1, Chung teaches an interconnection structure in a semiconductor device(Fig. 5), comprising:
a substrate(100);
a first insulating interlayer(120, ¶0089) on the substrate(100);
a first metal pattern(FP3, ¶0122) on the substrate(100) and passing through the first insulating interlayer(120, ¶0089);
a seed metal layer pattern(SEP3, ¶0118) surrounding a portion of a sidewall of the first metal pattern(FP3, ¶0122), a bottom of the first metal pattern(FP3, ¶0122), an upper sidewall of the first metal pattern(FP3, ¶0122) and an upper surface of the first metal pattern(FP3, ¶0122), the upper sidewall of the first metal pattern(FP3, ¶0122) and the upper surface of the first metal pattern(FP3, ¶0122) being exposed by the seed metal layer pattern(SEP3, ¶0118); and
a second metal pattern(VI1, ¶0100) directly contacting an uppermost surface of the seed metal layer pattern(SEP3, ¶0118), the upper sidewall of the first metal pattern(FP3, ¶0122), and the upper surface of the first metal pattern(FP3, ¶0122), the second metal pattern(VI1, ¶0100) filling at least a recess between the first insulating interlayer(120, ¶0089) and the first metal pattern(FP3, ¶0122).
Regarding claim 2, Chung teaches the interconnection structure in the semiconductor device of claim 1, wherein a resistance(resistance of tungsten, ¶0122) of the first metal pattern(FP3, ¶0122) is lower than a resistance(resistance of tungsten and boron, ¶0118) of the seed metal layer pattern(SEP3, ¶0118).
Regarding claim 4, Chung teaches the interconnection structure in the semiconductor device of claim 1, further comprising:
a barrier pattern(BP2, ¶0112) between a bottom of the seed metal layer pattern(SEP3, ¶0118) and a surface of the substrate(100).
Regarding claim 5, Chung teaches the interconnection structure in the semiconductor device of claim 4, wherein the barrier pattern(BP2, ¶0112) surrounds an outer surface of the seed metal layer pattern(SEP3, ¶0118).
Regarding claim 6, Chung teaches the interconnection structure in the semiconductor device of claim 1, wherein the seed metal layer pattern(SEP3, ¶0118) and the first metal pattern(FP3, ¶0122) include a same metal(tungsten, ¶0118, ¶0122).
Regarding claim 7, Chung teaches the interconnection structure in the semiconductor device of claim 1, wherein the seed metal layer pattern(SEP3, ¶0118) includes tungsten including boron(¶0118) or tungsten including boron and silicon, and the first metal pattern(FP3, ¶0122) includes bulk tungsten(¶0122).
Regarding claim 8, Chung teaches the interconnection structure in the semiconductor device of claim 1, wherein the upper surface of the first metal pattern(FP3, ¶0122) is coplanar with an upper surface of the first insulating interlayer(120, ¶0089), and
the uppermost surface of the seed metal layer pattern(SEP3, ¶0118) is lower than the upper surface of the first metal pattern(FP3, ¶0122).
Regarding claim 9, Chung teaches the interconnection structure in the semiconductor device of claim 1, further comprising:
a second insulating interlayer(130, ¶0188) on the first insulating interlayer(120, ¶0089), wherein the second metal pattern(VI1, ¶0100) passes through the second insulating interlayer(130, ¶0188).
Regarding claim 10, Chung teaches an interconnection structure in a semiconductor device(Fig. 5), comprising:
a substrate(GE);
a first insulating interlayer(120, ¶0089) on the substrate(GE), and the first insulating interlayer(120, ¶0089) including a first hole exposing a surface of the substrate(GE);
a seed metal layer pattern(SEP3, ¶0118) conformally on a sidewall of the first hole and a bottom of the first hole, the seed metal layer pattern(SEP3, ¶0118) having a first resistance(resistance of tungsten and boron, ¶0118);
a first metal pattern(FP3, ¶0122) on the seed metal layer pattern(SEP3, ¶0118) and filling the first hole, an upper sidewall of the first metal pattern(FP3, ¶0122) positioned above an uppermost surface of the seed metal layer pattern(SEP3, ¶0118), the first metal pattern(FP3, ¶0122) being exposed by the seed metal layer pattern(SEP3, ¶0118), the first metal pattern(FP3, ¶0122) having a second resistance(resistance of tungsten, ¶0122), and the second resistance(resistance of tungsten, ¶0122) being lower than the first resistance(resistance of tungsten and boron, ¶0118);
a second insulating interlayer(130, ¶0188) on the first insulating interlayer(120, ¶0089); and
a second metal pattern(VI1, ¶0100) passing through the second insulating interlayer(130, ¶0188),
the second metal pattern(VI1, ¶0100) directly contacting the uppermost surface of the seed metal layer pattern(SEP3, ¶0118), the upper sidewall of the first metal pattern(FP3, ¶0122), and an upper surface of the first metal pattern(FP3, ¶0122).
Regarding claim 11, Chung teaches the interconnection structure in the semiconductor device of claim 10, further comprising:
a barrier pattern(BP2, ¶0112) between a bottom of the seed metal layer pattern(SEP3, ¶0118) and the surface of the substrate(GE).
Regarding claim 12, Chung teaches the interconnection structure in the semiconductor device of claim 10, wherein
the seed metal layer pattern(SEP3, ¶0118) includes tungsten including boron(¶0112) or tungsten including boron and silicon, and
the first metal pattern(FP3, ¶0122) includes bulk tungsten(¶0122).
Regarding claim 13, Chung teaches the interconnection structure in the semiconductor device of claim 10, wherein the second metal pattern(VI1, ¶0100) has a single grain.
Regarding claim 14, Chung teaches the interconnection structure in the semiconductor device of claim 10, wherein
the upper surface of the first metal pattern(FP3, ¶0122) is coplanar with an upper surface of the first insulating interlayer(120, ¶0089), and
the uppermost surface of the seed metal layer pattern(SEP3, ¶0118) is lower than the upper surface of the first metal pattern(FP3, ¶0122).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (US 2023/0215930 A1).
Regarding claim 17, Chung teaches a semiconductor device(Fig. 5) comprising:
a substrate(100);
a nanosheet structure(CH1, SD1) on the substrate(100), the nanosheet structure including a nanosheet stack(CH1, ¶0145) and a semiconductor pattern(SD1, ¶0053) on sidewalls of the nanosheet stack(CH1, ¶0145), and the nanosheet stack(CH1, ¶0145) including silicon patterns(SP1, SP2, SP3, ¶0049) spaced apart in a vertical direction, the vertical direction being perpendicular to a surface of the substrate(100);
a gate structure(PO4, ¶0063) on the nanosheet stack(CH1, ¶0145), the gate structure(PO4, ¶0063) covering the nanosheet stack(CH1, ¶0145);
a first insulating interlayer(110, ¶0152) covering sidewalls of the gate structure(PO4, ¶0063) and on the semiconductor pattern(SD1, ¶0053), the first insulating interlayer(110, ¶0152) including a first hole exposing the semiconductor pattern(SD1, ¶0053);
a seed metal layer pattern(SEP1, ¶0106) conformally on a sidewall of the first hole and a bottom of the first hole, the seed metal layer pattern(SEP1, ¶0106) having a first resistance(resistance of tungsten and boron, ¶0106);
a first metal pattern(FP1, ¶0110) on the seed metal layer pattern(SEP1, ¶0106) and filling the first hole, an upper sidewall of the first metal pattern(FP1, ¶0110) positioned above an uppermost surface of the seed metal layer pattern(SEP1, ¶0106), the upper sidewall of the first metal pattern(FP1, ¶0110) being exposed by the seed metal layer pattern(SEP3, ¶0118), the first metal pattern(FP1, ¶0110) having a second resistance(resistance of tungsten, ¶0122), and the second resistance(resistance of tungsten, ¶0122) being lower than the first resistance(resistance of tungsten and boron, ¶0118),
a second insulating interlayer(130, ¶0089) on the first insulating interlayer(110, ¶0152);
a second metal pattern(VI1, ¶0100) passing through the second insulating interlayer(130, ¶0089),
the second metal pattern(VI1, ¶0100) directly contacting an upper surface of the first metal pattern(FP1, ¶0110).
Chung does not explicitly teach the second metal pattern(VI1, ¶0100) directly contacting the uppermost surface of the seed metal layer pattern(SEP1, ¶0106), the upper sidewall of the first metal pattern(FP1, ¶0110). Chung does teach the first metal pattern(FP1, ¶0110)and the seed metal layer pattern(SEP1, ¶0106) comprise a active contact(AC).
Chung teaches an gate contact(Fig. 7) wherein the second metal pattern(VI1, ¶0100) directly contacting the uppermost surface of the seed metal layer pattern(SEP3, ¶0118), the upper sidewall of the first metal pattern(FP3, ¶0122). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the active contact of Chung so that the second metal pattern directly contacting the uppermost surface of the seed metal layer pattern, the upper sidewall of the first metal pattern, as taught by the gate contact of Chung, in order to prevent the occurrence of void and prevent the increase of resistance of the active contact(¶0130).
Regarding claim 19, Chung teaches the semiconductor device of claim 17, further comprising:
a barrier pattern(BP2, ¶0112) surrounding an outer surface of the seed metal layer pattern(SEP1, ¶0106).
Regarding claim 20, Chung teaches the semiconductor device of claim 17, wherein the upper surface of the first metal pattern(FP1, ¶0110) is coplanar with an upper surface of the first insulating interlayer(110, ¶0152), and the uppermost surface of the seed metal layer pattern(SEP1, ¶0106) is lower than the upper surface of the first metal pattern(FP1, ¶0110).
Claims 3 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (US 2023/0215930 A1) in view of Chen et al. (US 2025/0051908 A1).
Regarding claim 3, Chung teaches the interconnection structure in the semiconductor device of claim 1, but is not relied on to teach the second metal pattern(VI1, ¶0100) has a single grain.
Chen the interconnection structure in a semiconductor device(Fig. 2F), wherein the second metal pattern(227, ¶0043) has a single grain(¶0044, ¶0004). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chung, so that the second metal pattern has a single grain, as taught by Chen, in order to lower the resistance of the second metal pattern(¶0030).
Regarding claim 18, Chung teaches the semiconductor device of claim 17, but is not relied on to teach the second metal pattern(VI1, ¶0100) has a single grain.
Chen the interconnection structure in a semiconductor device(Fig. 2F), wherein the second metal pattern(227, ¶0043) has a single grain(¶0044, ¶0004). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chung, so that the second metal pattern has a single grain, as taught by Chen, in order to lower the resistance of the second metal pattern(¶0030).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (US 2023/0215930 A1) in view of Cho et al. (US 2008/0003808 A1).
Regarding claim 15, Chung teaches the interconnection structure in the semiconductor device of claim 10, but is not relied on to teach the first insulating interlayer(120, ¶0089) and the second insulating interlayer(130, ¶0188) include different insulating materials, and the first insulating interlayer(120, ¶0089) has an etch selectivity with respect to the second insulating interlayer(130, ¶0188).
Cho teaches a interconnection structure in a semiconductor device(Fig. 5) wherein the first insulating interlayer(11, ¶0019) and the second insulating interlayer(12, ¶0019) include different insulating materials(¶0019), and the first insulating interlayer(11, ¶0019) has an etch selectivity(¶0008) with respect to the second insulating interlayer. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chung, so that the first insulating interlayer and the second insulating interlayer include different insulating materials, and the first insulating interlayer has an etch selectivity with respect to the second insulating interlayer, as taught by Cho, in order to prohibit the formation of O2 and prevent the undercut phenomenon of the metal line the first metal pattern(¶0019).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (US 2023/0215930 A1) in view of Zheng et al. (US 2017/0098605 A1).
Regarding claim 16, Chung teaches the interconnection structure in the semiconductor device of claim 10, but is not relied on to teach an etch stop layer between the first insulating interlayer(120, ¶0089) and the second insulating interlayer(130, ¶0188).
Zheng teaches an interconnection structure in a semiconductor device(Fig. 13) wherein an etch stop layer(140, ¶0024) between the first insulating interlayer(110, ¶0024) and the second insulating interlayer(150, ¶0024). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chung, to include an etch stop layer between the first insulating interlayer and the second insulating interlayer, as taught by Zheng, in order to stop the etching of the second insulating interlayer without over etching the first insulating interlayer(¶0024).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tada (US 5374849 A) Discloses an interconnection structure in a semiconductor device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA DYKES whose telephone number is (571)270-3161. The examiner can normally be reached M-F 9:30 am-5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LAURA M DYKES/Examiner, Art Unit 2892
Prosecution Insights