DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 and 7-10 have been amended.
Claims 1-20 have been examined.
The specification and drawing objections in the previous Office Action have been addressed and are withdrawn, except as otherwise indicated below.
The § 112 rejections in the previous Office Action have been addressed and are withdrawn.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 19, 2025 has been entered.
Specification
The disclosure is objected to because of the following informalities.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Appropriate correction is required. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which Applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 10-16, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication No. 2008/0034187 by Stempel et al. (hereinafter referred to as “Stempel”).
Regarding claim 1, Stempel discloses:
an apparatus comprising: an instruction sequencer configured to determine if a conditional branch opcode or an unconditional branch opcode is present and to anticipate a current prefetch buffer line based on a presence of the conditional branch opcode or the unconditional branch opcode… (Stempel discloses, at Figure 1 and related description, an instruction unit that controls instruction flow, which discloses an instruction sequencer. As disclosed at Figure 4 and related description, this involves determining if a branch is detected and if so, determining the branch target address, which discloses determining if a branch opcode is present and anticipating a current prefetch buffer line.);
a prefetcher coupled to the instruction sequencer, the prefetcher configured to retrieve program instructions (Stempel discloses, at Figure 1 and related description, a prefetch stage and fetch stage, which discloses a prefetcher configured to retrieve program instructions.); and
a prefetch buffer coupled to the prefetcher, the prefetch buffer configured to store the current prefetch buffer line (Stempel discloses, at Figure 1 and related description, an instruction cache, which discloses a prefetch buffer configured to store the current prefetch buffer line.).
Stempel does not explicitly disclose the aforementioned anticipating is “by examining one or more adjacent cache lines relative to a current cache line. However, Stempel discloses, at ¶ [0032], prefetching a next sequential cache line. It is evident that the next sequential cache line is then examined to determine whether the line includes a branch. See, e.g., Figure 4 and related description.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Stempel to search multiple cache lines in order to improve performance by requiring fewer accesses to cache.
Regarding claim 2, Stempel discloses the elements of claim 1, as discussed above. Stempel also discloses:
the instruction sequencer is further configured to read a plurality of opcodes over a plurality of prefetch buffer lines (Stempel discloses, at Figure 1 and related description, an instruction unit that dispatches instructions retrieved from the instruction cache, which discloses reading a plurality of opcodes over a plurality of prefetch buffer lines.).
Regarding claim 3, Stempel discloses the elements of claim 2, as discussed above. Stempel also discloses:
a bulk memory coupled to the prefetch buffer, the bulk memory configured to store the plurality of prefetch buffer lines (Stempel discloses, at ¶ [0022], external memory from which the instruction unit retrieves instructions, which discloses bulk memory.).
Regarding claim 5, Stempel discloses the elements of claim 3, as discussed above. Stempel also discloses:
a bulk memory controller coupled to the bulk memory, the bulk memory controller configured to manage read access and write access to the bulk memory (Stempel discloses, at Figure 1 and related description, a bus interface unit that provides a mechanism for transferring data to and from the memory, which discloses a bulk memory controller configured to manage read and write access.).
Regarding claim 10, Stempel discloses:
a method comprising: examining a current cache line from a plurality of cache lines (Stempel discloses, at Figure 1 and related description, an instruction unit that controls instruction flow, which discloses examining a current cache line.);
determining if a conditional branch opcode or an unconditional branch opcode is present (Stempel discloses, at Figure 4 and related description, determining if a branch is detected and if so, determining the branch target address, which discloses determining if a branch opcode is present.);
…sending an anticipatory address to a bulk memory to fetch one or more anticipatory program instructions Stempel discloses, at Figure 1 and related description, a prefetch stage and fetch stage, which discloses sending an address to fetch program instructions from bulk memory.); and
depositing the one or more anticipatory program instructions into a prefetch cache memory to augment an initial set of program instructions (Stempel discloses, at Figure 1 and related description, an instruction cache, which discloses storing prefetched instructions to a prefetch cache to augment initial instructions.).
Stempel does not explicitly disclose the aforementioned anticipating is “examining one or more adjacent cache lines relative to a current cache line. However, Stempel discloses, at ¶ [0032], prefetching a next sequential cache line. It is evident that the next sequential cache line is then examined to determine whether the line includes a branch. See, e.g., Figure 4 and related description.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Stempel to search multiple cache lines in order to improve performance by requiring fewer accesses to cache.
Regarding claim 11, Stempel discloses the elements of claim 10, as discussed above. Stempel also discloses:
the conditional branch opcode or the unconditional branch opcode is an operation code for defining an executable operation (Stempel discloses, at Figure 4 and related description, determining if a branch is detected, which discloses an opcode that is an operation code for defining an executable operation.).
Regarding claim 12, Stempel discloses the elements of claim 10, as discussed above. Stempel also discloses:
the anticipatory address is a bulk memory address (Stempel discloses, at ¶ [0022], external memory from which the instruction unit retrieves instructions, which discloses a bulk memory address.).
Regarding claim 13, Stempel discloses the elements of claim 10, as discussed above. Stempel also discloses:
using a cache replacement policy for depositing the one or more anticipatory program instructions (Stempel discloses, at Figure 1 and related description, an instruction cache, which discloses using a cache replacement policy.).
Regarding claim 14, Stempel discloses the elements of claim 13, as discussed above. Stempel also discloses:
the cache replacement policy uses one of the following: a sequential prefetching, a stride prefetching, a stream prefetching, a Markov prefetching, a demand-based prefetching, or a cache-line prefetching (Stempel discloses, at Figure 1 and related description, a prefetch stage and fetch stage, which discloses the cache replacement policy uses cache-line prefetching.).
Regarding claim 15, Stempel discloses the elements of claim 10, as discussed above. Stempel also discloses:
the plurality of cache lines is in the prefetcher cache memory (Stempel discloses, at Figure 1 and related description, an instruction cache, which discloses the plurality of cache lines in the prefetcher cache memory.).
Regarding claim 16, Stempel discloses the elements of claim 15, as discussed above. Stempel also discloses:
receiving the one or more anticipatory program instructions from the bulk memory (Stempel discloses, at Figure 1 and related description, storing instructions received via a bus interface unit in an instruction cache, which discloses receiving the instructions from bulk memory.).
Regarding claim 19, Stempel discloses the elements of claim 15, as discussed above. Stempel also discloses:
placing the initial set of program instructions into the plurality of cache lines (Stempel discloses, at Figure 1 and related description, storing instructions received via a bus interface unit in an instruction cache, which discloses placing the initial set of instructions in the cache.).
Regarding claim 20, Stempel discloses the elements of claim 19, as discussed above. Stempel also discloses:
one of the conditional branch opcode or the unconditional branch opcode is part of a program instruction within the current cache line (Stempel discloses, at Figure 4 and related description, determining if a branch is detected, which discloses determining if a branch opcode is part of a program instruction within the current cache line.).
Claim 4 and 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Stempel in view of US Publication No. 2003/0233530 by Boivie et al. (hereinafter referred to as “Boivie”).
Regarding claim 4, Stempel discloses the elements of claim 3, as discussed above. Stempel also discloses:
the instruction sequencer …configured to determine a presence of the conditional branch opcode or the unconditional branch opcode (Stempel discloses, at Figure 4 and related description, determining if a branch is detected, which discloses determining if a branch opcode is present.);
Stempel does not explicitly disclose the aforementioned determining involves an opcode comparator.
However, in the same field of endeavor (e.g., prefetch) Boivie discloses:
recognizing an opcode (Boivie discloses, at ¶ [0014] et seq., recognizing an opcode, which discloses an opcode comparator to do so.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Stempel to include Boivie’s opcode comparison in order to increase flexibility by providing an additional way to recognize branch instructions.
Regarding claim 7, Stempel discloses:
…examining a current cache line from a plurality of cache lines (Stempel discloses, at Figure 1 and related description, an instruction unit that controls instruction flow, which discloses a means for examining a current cache line.);
…determine if a conditional branch opcode or an unconditional branch opcode is present (Stempel discloses, at Figure 4 and related description, determining if a branch is detected and if so, determining the branch target address, which discloses means for determining if a branch opcode is present.);
…send an anticipatory address to a bulk memory to fetch one or more anticipatory program instructions (Stempel discloses, at Figure 1 and related description, a prefetch stage and fetch stage, which discloses means to send an address to fetch program instructions from bulk memory.); and
…deposit the one or more anticipatory program instructions into a prefetch cache memory to augment an initial set of program instructions (Stempel discloses, at Figure 1 and related description, an instruction cache, which discloses means to store prefetched instructions to a prefetch cache to augment initial instructions.).
Stempel does not explicitly disclose a non-transitory computer- readable medium storing computer executable code, operable on a device comprising at least one processor and at least one memory coupled to the at least one processor, wherein the at least one processor is configured to implement batch memory prefetching, the computer executable code comprising instructions, and examining one or more adjacent cache lines relative to the current cache line.
However, Stempel discloses, at ¶ [0032], prefetching a next sequential cache line. It is evident that the next sequential cache line is then examined to determine whether the line includes a branch. See, e.g., Figure 4 and related description.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Stempel to search multiple cache lines in order to improve performance by requiring fewer accesses to cache.
Also in the same field of endeavor (e.g., prefetching), Bovie discloses:
a non-transitory computer- readable medium storing computer executable code, operable on a device comprising at least one processor and at least one memory coupled to the at least one processor, the computer executable code comprising instructions (Bovie discloses, at ¶ [0013], the invention may be implemented with a conventional processor executing instructions stored in a machine readable medium such as a CD ROM.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Stempel to include the implementation disclosed by Bovie in order to improve flexibility regarding provisioning of Stempel’s system.
Regarding claim 8, Stempel discloses the elements of claim 7, as discussed above. Stempel also discloses:
means for using a cache replacement policy for depositing the one or more anticipatory program instructions (Stempel discloses, at Figure 1 and related description, an instruction cache, which discloses means for using a cache replacement policy.).
Regarding claim 9, Stempel discloses the elements of claim 8, as discussed above. Stempel also discloses:
instructions for causing the computer to receive the one or more anticipatory program instructions from the bulk memory (Stempel discloses, at Figure 1 and related description, storing instructions received via a bus interface unit in an instruction cache, which discloses receiving the instructions from bulk memory.);
instructions for causing the computer to use a …interface for receiving the one or more anticipatory program instructions (Stempel discloses, at Figure 1 and related description, storing instructions received via a bus interface unit in an instruction cache, which discloses using an interface to receive instructions.); and
instructions for causing the computer to place the initial set of program instructions into the plurality of cache lines (Stempel discloses, at Figure 1 and related description, storing instructions received via a bus interface unit in an instruction cache, which discloses placing the initial set of instructions in the cache.).
Stempel does not explicitly disclose the aforementioned access involves a serial interface.
However, in the same field of endeavor (e.g., memory) Kumar discloses:
a serial interface (Kumar discloses, at Figure 7 and related description, a quad serial peripheral interface (QSPI).).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Stempel to include Kumar’s QSPI in order to balance the well-known design considerations involved in transferring data between computer components. See, e.g., Kumar, ¶ [0004].
Claims 6, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Stempel in view of US Publication No. 2020/0192455 by Kumar et al. (hereinafter referred to as “Kumar”).
Regarding claim 6, Stempel discloses the elements of claim 5, as discussed above. Stempel also discloses:
…the bulk memory controller and the bulk memory… configured to allow the read access and the write access (Stempel discloses, at Figure 1 and related description, a bus interface unit that provides a mechanism for transferring data to and from the memory.).
Stempel does not explicitly disclose the aforementioned access involves a serial interface.
However, in the same field of endeavor (e.g., memory) Kumar discloses:
a serial interface (Kumar discloses, at Figure 7 and related description, a quad serial peripheral interface (QSPI).).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Stempel to include Kumar’s QSPI in order to balance the well-known design considerations involved in transferring data between computer components. See, e.g., Kumar, ¶ [0004].
Regarding claim 17, Stempel discloses the elements of claim 16, as discussed above. Stempel also discloses:
using a … interface for receiving the one or more anticipatory program instructions (Stempel discloses, at Figure 1 and related description, storing instructions received via a bus interface unit in an instruction cache, which discloses using an interface to receive instructions.).
Stempel does not explicitly disclose the aforementioned access involves a serial interface.
However, in the same field of endeavor (e.g., memory) Kumar discloses:
a serial interface (Kumar discloses, at Figure 7 and related description, a quad serial peripheral interface (QSPI).).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Stempel to include Kumar’s QSPI in order to balance the well-known design considerations involved in transferring data between computer components. See, e.g., Kumar, ¶ [0004].
Regarding claim 18, Stempel discloses the elements of claim 17, as discussed above. Stempel does not explicitly disclose the serial interface is an octal serial peripheral interface (OSPI) or a quad serial peripheral interface (QSPI).
However, in the same field of endeavor (e.g., memory) Kumar discloses:
a quad serial peripheral interface (Kumar discloses, at Figure 7 and related description, a quad serial peripheral interface (QSPI).).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Stempel to include Kumar’s QSPI in order to balance the well-known design considerations involved in transferring data between computer components. See, e.g., Kumar, ¶ [0004].
Response to Arguments
On pages 7-8 of the response filed December 19, 2025 (“response”), the Applicant argues, “The title is objected to because according to the Office Action, the title of "MEMORY PREFETCH MECHANISM BASED ON INSTRUCTION SETS" is not descriptive. No reason is given for this objection. Applicant respectively disagrees with this objection. The claims and the application disclosure are directed to memory prefetching which is part of the title. And, a memory prefetcher is dependent on instructions. For example, as recited in independent claim 1: "an instruction sequencer configured ... to anticipate a current prefetch buffer line based on a presence of the conditional branch opcode or the unconditional branch opcode..." Thus, the recited claim language of "prefetch" refers to memory and prefetch and the recited claim language of "opcode" is a synonym for the term instruction. Hence, Applicant respectfully submits that the title is descriptive of the recited claim 1 and all the other pending claims, and the title meets the requirement of MPEP §606. However, to facilitate prosecution, Applicant is open to changing the title of its application to Instruction-Based Memory Prefetching if there is strong insistence. Applicant invites the Examiner to call Applicant's attorney to discuss this issue in the hopes of a favorable resolution. Based on the explanation given herein, Applicant respectfully requests that the specification objection be withdrawn.”
Though fully considered, the Examiner respectfully disagrees. The title is not specific regarding what is the invention. Yes, the application and claims are “directed to” memory prefetching. However, the Applicant has not invented memory prefetching. Memory prefetching is an entire field of invention. The Applicant has purportedly invented something within the field of memory prefetching. However, the title provides no notice as to what the invention may be. Memory prefetching “based on instruction sets” does not meaningfully narrow things down. All memory prefetching is based on instruction sets. Similarly, “Instruction-based” memory prefetching describes essentially all memory prefetching. Therefore, the title lacks the requisite specificity regarding what it is the Applicants consider to be the invention. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On page 11 of the response the Applicant argues, “in Stempel, sequential addresses for fetching and prefetching are referenced relative to a first address A, in units of bytes. In particular, the prefetch register is loaded with an address of a next sequential cache line (e.g., A+0x20) relative to the first address A. However, there is no disclosure or even suggestion of "examining one or more adjacent cache lines relative to a current cache line", as recited in the amended pending claims of the present application. There is no examination of adjacent cache lines relative to a current cache line in Stempel. Instead, Stempel discloses directing an address of a next sequential cache line into a prefetch register to allow a prefetch operation to flow through a fetch stage pipeline.”
Though fully considered, the Examiner respectfully disagrees. Stempel discloses searching for a taken branch instruction in a given cache line. See, e.g., Figure 4 and related description, specifically ¶ [0045]. If no such branch is found in the cache line, the next sequential cache line is retrieved. See, e.g., ¶ [0046]. That cache line is then examined to detect the presence of a taken branch, and so on. See, e.g., ¶ [0049]. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On page 12 of the response the Applicant argues, “there is no disclosure or even suggestion in Boivie of "examining one or more adjacent cache lines relative to a current cache line", as recited in the amended pending claims of the present application.”
As Boivie is not cited as teaching these features, the Applicant’s arguments are deemed unpersuasive.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure.
US 6101577 by Tran discloses examining multiple cache lines.
US 20080209131 by Kornegay discloses searching all lines of a cache.
US 20180060073 by Havlir discloses examining the next sequential cache line for prediction.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/Primary Examiner, Art Unit 2183
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