CTNF 18/761,895 CTNF 78914 DETAILED ACTION 07-03-aia AIA 15-10-aia 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This Office Action is in response to the communications dated 02/05/2026. Claims 1-20 are pending in this application. Acknowledges 2. Receipt is acknowledged of the following items from the Applicant. Information Disclosure Statements (IDS) filed on 07/02/2024, and 02/05/2026. The references cited on the PTOL 1449 form have been considered. Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609. Specification 06-31 AIA 3. The specification has been checked to the extent necessary to determine the presence of possible minor errors. However, the applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA 5. Claim s 9, 11-13, 15, and 16 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Jagannathan et al. (US 2013/0260549) Regarding claim 9, Jagannathan discloses an apparatus comprising: a semiconductor substrate 10 (see fig. 14) having a plurality of active regions 12A, 12B each surrounded by a STI region 20; a plurality of MOS transistors formed in the plurality of active regions, each of the plurality of MOS transistors including source/drain regions 16A & 46A, 16B & 46B, an epitaxial layer 16A, 16B in the source/drain regions (see para. 0049), a channel region between the source/drain regions, and a gate electrode 36A-40A covering the channel region with a gate insulating film 31A/32A, 31B/32B interposed therebetween; a side wall film 52A, 52B covering a side of the gate electrode; a liner film 54 continuously covering the gate electrode and the source/drain regions of each of the plurality of MOS transistors and the STI region 20, wherein the side wall film 52A, 52B is between a side wall portion of the liner film 56 and the side of the gate electrode 36A-40A, 36B-40B; 16econd active region 12B is in contact with the source/drain regions 16B & 46B. Regarding claim 11, Jagannathan discloses the apparatus according to claim 9, wherein the gate electrode further comprises a polysilicon film 40A, or 140L and a tungsten film on the gate insulating film. See figs. 7-17, and para. 0067. Regarding claim 12, Jagannathan discloses the apparatus according to claim 11, wherein the gate electrode further comprises a metal gate between the gate insulating film and the polysilicon film. See paras. 0067-0069. Regarding claim 13, Jagannathan discloses the apparatus according to claim 9, further comprising a tensile/compressive film 56, 58 (fig. 14) covering the liner film 54 such that the tensile/compressive film 56, 85 covers the source/drain regions of each of the plurality of MOS transistors and the STI region with the liner film interposed therebetween. See fig. 14. Regarding claim 15, Jagannathan discloses the apparatus of claim 9, wherein the source/drain regions 16B & 46B in the second active region 12B are covered by the epitaxial layer 16B in the second active region, and the source/drain regions 16A & 46A in the first active region 12A are covered by the epitaxial layer 16A in the first active region and the liner film 54. See fig. 14. Regarding claim 16, Jagannathan discloses the apparatus of claim 9, wherein the LDD regions have an LDD/HALO structure including a HALO region. See fig. 14 . Claim Rejections - 35 U.S.C. § 103 07-20-aia AIA 6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA 7. Claim s 1-3, and 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Richter et al. (US 2009/0001453) in view of Wang et al. (US 7,642,607) . Regarding claim 1, Richter discloses an apparatus comprising: a semiconductor substrate 501 (see fig. 4C) having a plurality of active regions 504, 604 each surrounded by a STI region 503 comprising a first insulating material (well known and commonly used of silicon dioxide) ; a plurality of MOS transistors 502, 602 formed in the plurality of active regions 504, 604, respectively, each of the plurality of MOS transistors 502, 602 including source/drain regions 507/508, 607/608, a channel region between the source/drain regions, and a gate electrode 506, 606 covering the channel region with a gate insulating film 505, 605 interposed therebetween; a liner film 550 continuously covering the gate electrode 506, 606 and the source/drain regions 507/508, 607/608 of each of the plurality of MOS transistors and the STI region 503, the liner film 550 comprising a second insulating material (etch stop layer of silicon nitride, para. 0085) different from the first insulating material; and a tensile/compressive film 551, 557 (paras. 0087, 0092) covering the liner film 550 such that the tensile/compressive film 557 covers the source/drain regions 507/508, 607/608 of each of the plurality of MOS transistors and the STI region 503 with the liner film 550 interposed therebetween, wherein the plurality of active regions includes first and second active regions 504, 506, wherein the each of the plurality of MOS transistors 502, 602 further includes LDD regions (directly underneath spacers 512, 612, see fig. 4C) between each of the source/drain regions and the channel region. Richter fails to teach: wherein the LDD regions of one of the plurality of MOS transistors in the first active region 504 is shorter in length than the LDD regions of another of the plurality of MOS transistors in the second active region 604. Wang discloses : An apparatus comprising a plurality of MOS transistors 100, 200 formed in a plurality of active regions 40 (see fig. 16), wherein the each of the plurality of MOS transistors 100, 200 further includes LDD regions 130, 230 between each of source/drain regions 111 &124, and 234 and the channel region (see col. 4, lines 25-30; col. 6, lines 1-3), wherein the LDD regions 130 of the MOS transistor 100 in the first active region 40 is shorter in length than the LDD regions 230 of the MOS transistor 200 in the second active region 40. It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Richter so that the LDD regions of the transistor(s) in the first active region would be shorter in length than the LDD regions of the MOS transistor(s) in the second active region, as that taught by Wang, in order to significantly improve the drive current of the MOS transistor. See col. 6, lines 14-20 of Wang. Regarding claim 2, Richter/Wang discloses the apparatus as claimed in wherein the liner film 550 includes a side wall section covering a side surface of the gate electrode 506/606, and wherein the tensile/compressive film 557 includes a side wall section covering the side wall section of the liner film 550 without an insulating film comprising the first insulating material interposed therebetween. See fig. 4C. Regarding claim 3, Richter/Wang discloses the apparatus as claimed in claim 2, further comprising: a side wall film 512/612 between the side wall section of the liner film 550 and the side surface of the gate electrode 506/606, wherein the LDD regions of the first active region are in contact with the side wall film and the LDD regions of the second active region are in contact with side wall film and the liner film. See fig. 4c of Richter and fig. 16 of Wang. Regarding claim 6, Richter/Wang discloses the apparatus as claimed in claim 1, wherein the first insulating material 503 includes a silicon oxide. Note: it would have been well known and common in the art that shallow trench isolation region (STI) is filled with an oxide material, primarily silicon dioxide. Regarding claim 7, Richter/Wang discloses the apparatus as claimed in claim 1, wherein the second insulating material 550 includes a silicon nitride. Para. 0085: etch stop layer 550 of silicon nitride. Regarding claim 8, Richter/Wang discloses the apparatus as claimed in claim 1, wherein the source/drain regions in the first active region are longer in length than the source/drain regions in the second active region. See fig. 16 of Wang . 07-21-aia AIA 8. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Jagannathan et al. (US 2013/0260549) in view of Wang et al. (US 7,642,607) . Regarding claim 10, Jagannathan discloses the apparatus comprising all claimed limitations, as discussed above, except for wherein the LDD regions of one of the plurality of MOS transistors in the first active region is shorter in length than the LDD regions of another of the plurality of MOS transistors in the second active region. Wang discloses : An apparatus comprising a plurality of MOS transistors 100, 200 formed in a plurality of active regions 40 (see fig. 16), wherein the each of the plurality of MOS transistors 100, 200 further includes LDD regions 130, 230 between each of source/drain regions 111 &124, and 234 and the channel region (see col. 4, lines 25-30; col. 6, lines 1-3), wherein the LDD regions 130 of the MOS transistor 100 in the first active region 40 is shorter in length than the LDD regions 230 of the MOS transistor 200 in the second active region 40. It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Jagannathan so that the LDD regions of the transistor(s) in the first active region would be shorter in length than the LDD regions of the MOS transistor(s) in the second active region, as that taught by Wang, in order to significantly improve the drive current of the MOS transistor. See col. 6, lines 14-20 of Wang . Allowable Subject Matter 9. Claims 4, 5, and 14 are allowable. Claims 4, 5, and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed apparatus (in addition to the other limitations in the claim) comprising: Claim 4: The apparatus wherein each of the plurality of the MOS transistors are formed in either one of the first and second active regions, respectively, and wherein a pitch of the gate electrodes of the plurality of MOS transistors in the first active region is smaller than a pitch of the gate electrodes of the plurality of MOS transistors in the second active region. Claim 5: The apparatus further comprising a memory cell array including a plurality of memory cells arranged in a predetermined pitch, wherein the pitch of the gate electrodes of the plurality of MOS transistors in the first active region is substantially the same as the predetermined pitch. Claim 14: The apparatus wherein a portion of the STI region is covered by the gate insulating film, and another portion of the STI region is covered by the liner film and the side wall film. Allowance / Reasons for Allowance 12-151-07 AIA 07-97 12-51-07 10. Claim s 17-20 are allowed. The following is an examiner’s statement of reason for allowance: None of the references of record teaches or suggests the claimed semiconductor device (in combination set forth in the claim) comprising: a second circuit coupled to the first circuit, the second circuit comprising a second plurality of MOS transistors, wherein the first plurality of MOS transistors is in a first plurality of active regions and the second plurality of MOS transistors is in a second plurality of active regions, each of the first plurality and second plurality of active regions surrounded by a STI region, wherein each MOS transistor of the first plurality and second plurality of MOS transistors includes: LDD regions between the source/drain regions and the channel region, and wherein the LDD regions of the first plurality of MOS transistors in the first active region is shorter in length than the LDD regions of another of the plurality of MOS transistors in the second active region. Conclusion 11. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)). A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633. /DAO H NGUYEN/Primary Examiner, Art Unit 2818 May 5, 2026 Application/Control Number: 18/761,895 Page 2 Art Unit: 2818 Application/Control Number: 18/761,895 Page 3 Art Unit: 2818 Application/Control Number: 18/761,895 Page 4 Art Unit: 2818 Application/Control Number: 18/761,895 Page 5 Art Unit: 2818 Application/Control Number: 18/761,895 Page 6 Art Unit: 2818 Application/Control Number: 18/761,895 Page 7 Art Unit: 2818 Application/Control Number: 18/761,895 Page 8 Art Unit: 2818 Application/Control Number: 18/761,895 Page 9 Art Unit: 2818 Application/Control Number: 18/761,895 Page 10 Art Unit: 2818
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