DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8, 11-13, and 15-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (U.S. Publication No. 2022/0013502 A1; hereinafter Lee)
With respect to claim 1, Lee discloses a semiconductor package, comprising: a plurality of first semiconductor chips [110C/120C] stacked on each other; a second semiconductor chip [130C] including a front surface and disposed on the plurality of first semiconductor chips, wherein the front surface of the second semiconductor chip faces the plurality of first semiconductor chips, and wherein the second semiconductor chip further includes a first dummy pad [146DP] located on a back surface, opposite to the front surface, of the second semiconductor chip; and a third semiconductor chip [140C] including a front surface and disposed on the back surface of the second semiconductor chip, wherein the front surface of the third semiconductor chip faces the second semiconductor chip, wherein the third semiconductor chip further includes a second dummy pad [146DP] located on the front surface of the third semiconductor chip, wherein the first dummy pad is disposed on at least a part of a back surface edge region [DPR2] that is adjacent to a side surface of the second semiconductor chip, wherein the second dummy pad is disposed on at least a part of a front surface edge [DPR2] region that is adjacent to a side surface of the third semiconductor chip, and wherein the first dummy pad and the second dummy pad are bonded to each other (see Figure 12; ¶[0100]).
With respect to claim 2, Lee discloses wherein: the first dummy pad is of a plurality of first dummy pads [DP], the plurality of first dummy pads continuously extend along the back surface edge region of the second semiconductor chip, the second dummy pad is of a plurality of second dummy pads, and the plurality of second dummy pads continuously extend along the front surface edge region of the third semiconductor chip (See Figure 2 and 12).
With respect to claim 3, Lee discloses wherein: the first dummy pad is of a plurality of first dummy pads [DP], the plurality of first dummy pads are arranged along the back surface edge region of the second semiconductor chip, the second dummy pad is of a plurality of second dummy pads, and the plurality of second dummy pads are arranged along the front surface edge region of the third semiconductor chip (see Figure 2 and 12).
With respect to claim 4, Lee discloses wherein: the first dummy pad is of a plurality of first dummy pads [DP], the plurality of first dummy pads are respectively disposed in a corner region of the back surface edge region that is adjacent to a corner formed by two side surfaces of the second semiconductor chip, the second dummy pad is of a plurality of second dummy pads, and the plurality of second dummy pads are respectively disposed in a corner region of the front surface edge region that is adjacent to a corner formed by two side surfaces of the third semiconductor chip (see Figure 2, 4 and 12).
With respect to claim 5, Lee discloses wherein: the first dummy pad is of a plurality of first dummy pads [DP], the plurality of first dummy pads are continuously disposed along regions that are adjacent to two side surfaces, which face each other, of the second semiconductor chip, the second dummy pad is of a plurality of second dummy pads, and the plurality of second dummy pads are continuously disposed along regions adjacent to two side surfaces, which face each other, of the third semiconductor chip (see Figure 2, 4 and 12).
With respect to claim 6, Lee discloses wherein: the second semiconductor chip further comprises a first insulating layer [132D] disposed on a side surface of the first dummy pad, the third semiconductor chip further comprises a second insulating layer [142B] disposed on a side surface of the second dummy pad, and the first insulating layer and the second insulating layer are bonded to each other (See Figure 12).
With respect to claim 7, Lee discloses wherein: the second semiconductor chip comprises a first connection pad [136MP] located on the front surface thereof, a second connection pad [146MP] located on the back surface thereof and spaced apart from the first dummy pad, and a first through via [138A] electrically connecting the first connection pad and the second connection pad to each other, the third semiconductor chip further comprises a third connection pad [146MP] located on the front surface thereof and spaced apart from the second dummy pad, and the second connection pad and the third connection pad are bonded to each other (see Figure 4 and 12).
With respect to claim 8, Lee discloses wherein: each of the plurality of first semiconductor chips comprises a fourth connection pad [114/126MP] located on a front surface of each of the plurality of first semiconductor chips, a fifth connection pad [126MP/136MP] located on a back surface opposite to the front surface of each of the plurality of first semiconductor chips, and a second through via [118A/128A] electrically connecting the fourth connection pad and the fifth connection pad to each other, and the fourth connection pad of a first first semiconductor chip of the plurality of first first semiconductor chips is bonded to the fifth connection pad of a second first semiconductor chip of the plurality of first semiconductor chips (See Figure 12).
With respect to claim 11, Lee discloses a molding material [160] for molding the plurality of first semiconductor chips, the second semiconductor chip, and the third semiconductor chip (see Figure 13)
With respect to claim 12, Lee discloses wherein: a back surface of the third semiconductor chip, which is opposite to the front surface of the third semiconductor chip, is exposed by the molding material (See Figure 13; exposed to [700]).
With respect to claim 13, Lee discloses a semiconductor package, comprising: a first semiconductor chip [110c] including a first dummy pad [126DP] located on a back surface thereof; and a plurality of second semiconductor chips [120C/130C] disposed on a back surface of the first semiconductor chip so that each front surface of each of the plurality of second semiconductor chips faces the first semiconductor chip, wherein a lowermost second semiconductor chip, which is disposed at the lowest position among the plurality of second semiconductor chips, includes a second dummy pad [126DP] located on the front surface of the second semiconductor chip, wherein the second dummy pad is disposed on at least a part of a front surface edge region that is adjacent to a side surface of the lowermost second semiconductor chip, and wherein the first dummy pad is bonded to the second dummy pad by overlapping each other (see Figure 12).
With respect to claim 15, Lee discloses wherein: the first semiconductor chip is a logic chip, and the lowermost second semiconductor chip is a high bandwidth memory chip (see ¶[0103]).
With respect to claim 16, Lee discloses wherein: the first semiconductor chip further comprises a first insulating layer [112D] disposed on a side surface of the first dummy pad, the lowermost second semiconductor chip further comprises a second insulating layer [122B] disposed on a side surface of the second dummy pad, and the first insulating layer and the second insulating layer are bonded to each other (See Figure 12).
With respect to claim 17, Lee discloses wherein: the first semiconductor chip comprises a first connection pad [114] located on a front surface of the first semiconductor chip, which is opposite to the back surface of the first semiconductor chip, a second connection pad [118B/126MP] located on the back surface of the first semiconductor chip and spaced apart from the first dummy pad, and a first through via [118A] electrically connecting the first connection pad and the second connection pad to each other, each of the plurality of second semiconductor chips comprises a third connection pad [126MP] located on the front surface of each of the plurality of second semiconductor chips, a fourth connection pad [136MP] disposed on a back surface of each of the plurality of second semiconductor chips, and a second through via [128A] electrically connecting the third connection pad and the fourth connection pad to each other, and the second connection pad of the first semiconductor chip and the third connection pad of the lowermost second semiconductor chip are bonded to each other.
With respect to claim 18, Lee discloses wherein: the third connection pad of a first second semiconductor chip of the plurality of second semiconductor chips is bonded to the fourth connection pad of a second second semiconductor chip of the plurality of second semiconductor chips (See Figure 12).
With respect to claim 19, Lee discloses a molding material [160] disposed on the first semiconductor chip to mold the plurality of second semiconductor chips (see figure 12).
With respect to claim 20, Lee discloses a semiconductor package, comprising: a first semiconductor chip [110C] having opposing front and back surfaces, and comprising a first connection pad [114] located on the front surface thereof, a second connection pad [126MP] and a first dummy pad [126DP] located on the back surface thereof and spaced apart from each other, and a first through via [118A] electrically connecting the first connection pad and the second connection pad to each other; and a second semiconductor chip [120C] including a front surface and disposed on the back surface of the first semiconductor chip, wherein the front surface of the second semiconductor chip faces the first semiconductor chip, and wherein the second semiconductor chip further includes a third connection pad [126MP] and a second dummy pad [126DP] spaced apart from each other on the front surface of the second semiconductor chip, wherein the first dummy pad is disposed on at least a part of a back surface edge region that is adjacent to a side surface of the first semiconductor chip, wherein the second dummy pad is disposed on at least a part of a front surface edge region that is adjacent to a side surface of the second semiconductor chip (see Figure 2), wherein the first dummy pad and the second dummy pad are bonded to each other, and wherein the second connection pad and the third connection pad are bonded to each other (See Figure 2, 4 and 12).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Jee et al. (U.S. Publication No. 2023/0074933 A1; hereinafter Jee)
With respect to claim 9, Lee discloses wherein: a thickness of the third semiconductor chip is larger than each of a thickness of each of the plurality of first semiconductor chips and a thickness of the second semiconductor chip (see Figure 12). Lee fails to disclose the third semiconductor chip is a dummy chip. In the same field of endeavor, Jee teaches a stack semiconductor package wherein the third semiconductor chip [402] is a dummy chip (see Figure 2A) Implementation of a dummy chip within the package of Lee, as taught by Jee increases rigidity of the overall device, thereby preventing bending (see ¶[0066]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 10, the combination of Lee and Jee discloses wherein: the second semiconductor chip [402] is a dummy chip (see Figure 2A; stack of dummy chips).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kim et al. (U.S. Publication No. 2021/0005576 A1; hereinafter Kim)
With respect to claim 14, Lee fails to disclose wherein: the width of the first semiconductor chip is wider than the width of the lowermost second semiconductor chip. In the same field of endeavor, Kim teaches wherein: the width of the first semiconductor chip [100] is wider than the width of the lowermost second semiconductor chip (see Figure 1; ¶[0042]).
Implementation of a wider first semiconductor chip as taught by Kim allows for a structurally more stable base and increased real estate for via structures (see Kim ¶[0047]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN HAN whose telephone number is (571)270-7546. The examiner can normally be reached 9.00-5.00PM PST.
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/JONATHAN HAN/Primary Examiner, Art Unit 2818
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