Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-20 are rejected under 35 U.S.C. l12(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1, 4, 9, 11, 15 recites “the encoded weights” where the scope related to said limitation is deemed indefinite. Because, previous limitation recites “a plurality of encoded weights” clearly indicate multiple encoded weights whereas “the encoded weights” is very specific and not clear and deemed indefinite.
Similarly, Claim 1, 9 recites “the memory cells” where the scope related to said limitation is deemed indefinite. Because, previous limitation recites “a plurality of memory cells” clearly indicate multiple memory cells whereas “the memory cells” is very specific and not clear and deemed indefinite.
Also in claim 8, 11, 14-15 recite “the weights” where the scope related to said limitation is deemed indefinite. Because, previous limitation recites “a plurality of weights” and “a plurality of encoded weights” clearly indicate multiple weights or encoded weights where the specific limitation “the weights” is totally unclear and indefinite.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Dreesen et al. (US Pub # 2022/0101914).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Dreesen et al. teach a memory device, comprising: an encoder circuit configured to convert a first bit of each of a plurality of weights into a sign bit to generate a plurality of encoded weights according to flag data (see Fig. 1-14, paragraph 0023-0024, 0029-0039, 0043-0055, 0060-0062, 0090-0104 where weight value is encoded by weight bits 111A-111D); a memory array comprising a plurality of memory cells, wherein the memory cells arranged in a same column are configured to store bits, of the encoded weights and the flag data, having the same index number (see Fig. 1-14, paragraph 0023-0024, 0029-0039, 0043-0055, 0060-0062, 0090-0104, array circuit 1101), wherein the memory array is configured to perform a compute-in-memory (CIM) operation to the encoded weights and a plurality of inputs to generate a plurality of CIM results, wherein each of the plurality of CIM results corresponds to a column of the memory array (see Fig. 1-14, paragraph 0023-0024, 0029-0039, 0043-0055, 0060-0062, 0090-0101); and an accumulator circuit configured to decode the plurality of CIM results according to the flag data to generate a plurality of decoded CIM results (see Fig. 1-14, paragraph 0023-0024, 0029-0039, 0043-0055, 0060-0062, 0090-0104 where compute memory accumulate operations).
Even though Dreesen et al. teaches encoding the weights value but silent exclusively about encoder circuits. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Dreesen et al. where encoder must be there to encode the weight value in order to reduce variation and improve accuracy of in-memory computation (see paragraph 0028).
Regarding claim 2, Dreesen et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Dreesen et al. further teach, wherein the flag data indicates a first index number, wherein the encoder circuit is further configured to convert the first bit having the first index number into the sign bit and add a value of the first bit to a second bit of each of a plurality of weights, and wherein the second bit has a second index number that is greater than the first index number by one (see Fig. 1-14, paragraph 0023-0024, 0029-0039, 0043-0055, 0060-0062).
Regarding claim 3, Dreesen et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Dreesen et al. further teach, wherein the plurality of weights are in a two?s complement format and the plurality of encoded weights are in a dual sign bit format that has two sign bits (see Fig. 1-14, paragraph 0023-0024, 0029-0039, 0043-0055, 0060).
Regarding claim 4, Dreesen et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Dreesen et al. further teach wherein index numbers of bits having values of one in the flag data correspond to index numbers of sign bits of the encoded weights (see Fig. 1-14, paragraph 0023-0024, 0029-0039, 0043-0055).
Regarding claim 5, Dreesen et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Dreesen et al. further teach, wherein the memory array is further configured to generate a plurality of currents corresponding to the columns of the memory array according to the CIM operation, wherein the memory device further comprises: an analog-to-digital converter configured to perform an analog-to-digital conversion to the plurality of currents to generate the plurality of CIM results (see Fig. 1-14, paragraph 0023-0024, 0029-0039, 0043-0055, 0060-0062, 0090-0091).
Regarding claim 6, Dreesen et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Dreesen et al. further teach, further comprising a register circuit configured to retrieve the flag data from the memory array, wherein the accumulator circuit comprises: a plurality of recovery circuits configured to decode the plurality of CIM results according to the flag data from the register circuit to generate the plurality of decoded CIM results; and a shifter-and-adder circuit configured to accumulate the plurality of decoded CIM results to generate a final result (see Fig. 1-14, paragraph 0023-0024, 0029-0039, 0043-0055, 0060-0062, 0090-0101).
Regarding claim 7, Dreesen et al. teach all claimed subject matter as applied in prior rejection of claim 6 on which this claim depends.
Dreesen et al. further teach, wherein each of the plurality of recovery circuits is configured to decode a corresponding CIM result of the plurality of CIM results according to a corresponding flag bit of the flag data, wherein the each of the plurality of recovery circuits comprises: a first transmission gate configured to turn on, in response to the corresponding flag bit having a value of zero, to output the corresponding CIM result as a corresponding one of the plurality of decoded CIM results (see Fig. 1-14, paragraph 0023-0024, 0029-0039, 0043-0055); an inverter configured to invert the corresponding CIM result to generate an inversion; and a second transmission gate configured to turn on, in response to the corresponding flag bit having a value of one, to output the inversion as the corresponding one of the plurality of decoded CIM results (see Fig. 1-14, paragraph 0023-0024, 0029-0039, 0043-0055, 0060-0062, 0090-0100).
Regarding claim 8, Dreesen et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Dreesen et al. further teach, wherein an index number of the sign bit is set equal to a number ?N?, wherein a value of ?2M-2N?is less than a maximum value of the plurality of weights, wherein the number ?M? corresponds to the largest index number of the bits of the weights (see Fig. 1-14, paragraph 0023-0024, 0029-0039, 0043-0055, 0060-0062).
Regarding independent claim 9, Dreesen et al. teach a system, comprising: an encoder circuit configured to convert a plurality of weights in form of twos complement into a plurality of encoded weights in form of dual sign bit according to flag data, wherein each of the encoded weights has two sign bits (see Fig. 1-14, paragraph 0023-0024, 0029-0039, 0043-0055, 0060-0062, 0090-0104 where weight value is encoded by weight bits 111A-111D); a memory array comprising a plurality of memory cells, wherein a first row of the memory cells is configured to store the flag data and a plurality of second rows of the memory cells are configured to store the encoded weights, wherein the memory array is configured to perform dot-product operations to the encoded weights and a plurality of inputs on word lines of the memory array to generate a plurality of dot-product results on bit lines of the memory array (see Fig. 1-14, paragraph 0023-0024, 0029-0039, 0043-0055, 0060-0062, 0090-0104, array circuit 1101); an analog-to-digital converter circuit configured to convert the dot-product results into a plurality of digital dot-product results (see Fig. 1-14, paragraph 0023-0024, 0029-0039, 0043-0055, 0060-0062, 0090-0104, converter 1003); and an accumulator circuit configured to decode the digital dot-product results according to the flag data to generate a plurality of decoded dot-product results (see Fig. 1-14, paragraph 0023-0024, 0029-0039, 0043-0055, 0060-0062, 0090-0104 where compute memory accumulate operations).
Even though Dreesen et al. teaches encoding the weights value but silent exclusively about encoder circuits. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Dreesen et al. where encoder must be there to encode the weight value in order to reduce variation and improve accuracy of in-memory computation (see paragraph 0028).
Regarding claim 10, Dreesen et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Dreesen et al. further teach, the encoder circuit is further configured to convert a first bit of each of the plurality of weights into a sign bit and add the value of the first bit to a second bit of each of the plurality of weights, wherein the index number of the second bit is greater than the index number of the first bit by one (see Fig. 1-14, paragraph 0023-0024, 0029-0039, 0043-0055, 0060).
Regarding claim 11, Dreesen et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Dreesen et al. further teach, wherein a first sign bit of the two sign bits is a most significant bit of each of the encoded weights, wherein the system further comprises: a processor configured to determine an index number of a second sign bit of the two sign bits, wherein a value of ?2M-2N?is less than a maximum value of the plurality of weights, wherein the number ?M? corresponds to the largest index number of the bits of the weights and the number ?N? corresponds to the index number (see Fig. 1-14, paragraph 0023-0024, 0029-0039, 0043-0055, 0060-0062, 0090-0101).
Regarding claim 12, Dreesen et al. teach all claimed subject matter as applied in prior rejection of claim 11 on which this claim depends.
Dreesen et al. further teach, wherein the processor is further configured to encode the plurality of weights into a plurality of test encoded weights with the second sign bit having a test index number, wherein the processor is further configured to determine the test index number as the index number according to sparsity of the plurality of test encoded weights (see Fig. 1-14, paragraph 0023-0024, 0029-0039, 0043-0055, 0060-0062, 0090).
Regarding claim 13, Dreesen et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Dreesen et al. further teach, wherein the accumulator circuit comprises: a plurality of recovery circuits, wherein each of the plurality of recovery circuits comprises: an inverter configured to receive a first digital dot-product result of the plurality of digital dot-product results and generate an inversion of the first digital dot-product result; a first switch configured to turn on, in response to a first bit of the flag data having a value one, to transmit the inversion as an output of the recovery circuit; and a second switch configured to turn on, in response to the first bit of the flag data having a value zero, to transmit the first digital dot-product result as the output of the recovery circuit (see Fig. 1-14, paragraph 0023-0024, 0029-0039, 0043-0055, 0060-0062, 0090-0103).
Regarding claim 14, Dreesen et al. teach all claimed subject matter as applied in prior rejection of claim 13 on which this claim depends.
Dreesen et al. further teach, wherein the accumulator circuit further comprises: a shifter-and-adder circuit configured to shift and add the outputs of the plurality of recovery circuits to generate a multiply-and-accumulate result of the weights and the inputs (see Fig. 1-14, paragraph 0023-0024, 0029-0039, 0043-0055).
Regarding independent claim 15, Dreesen et al. teach a method, comprising: converting a magnitude bit of each of a plurality of weights into a sign bit according to flag data to generate a plurality of encoded weights, wherein the flag data indicating an index number of the magnitude bit (see Fig. 1-14, paragraph 0023-0024, 0029-0039, 0043-0055, 0060-0062, 0090-0104 where weight value is encoded by weight bits 111A-111D); performing a plurality of compute-in-memory (CIM) operations to the encoded weights and a plurality of inputs transmitted to a memory array storing the weights to generate a plurality of CIM results; decoding the CIM results to generate a plurality of decoded CIM results (see Fig. 1-14, paragraph 0023-0024, 0029-0039, 0043-0055, 0060-0062, 0090-0104, array circuit 1101); and accumulating the decoded CIM results to generate a final result (see Fig. 1-14, paragraph 0023-0024, 0029-0039, 0043-0055, 0060-0062, 0090-0104 where compute memory accumulate operations).
Even though Dreesen et al. teaches encoding the weights value but silent exclusively about encoder circuits. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Dreesen et al. where encoder must be there to encode the weight value in order to reduce variation and improve accuracy of in-memory computation (see paragraph 0028).
Regarding claim 16, Dreesen et al. teach all claimed subject matter as applied in prior rejection of claim 15 on which this claim depends.
Dreesen et al. further teach, further comprising: converting a magnitude bit, having a test index number, of each of the plurality of weights into the sign bit to generate a plurality of test encoded weights; and determining the test index number as the index number according to sparsity of the plurality of test encoded weights (see Fig. 1-14, paragraph 0023-0024, 0029-0039, 0043-0055, 0060-0062).
Regarding claim 17, Dreesen et al. teach all claimed subject matter as applied in prior rejection of claim 15 on which this claim depends.
Dreesen et al. further teach, further comprising: determining the index number according to a maximum value of the plurality of weights (see Fig. 1-14, paragraph 0023-0024, 0029-0039, 0043-0051).
Regarding claim 18, Dreesen et al. teach all claimed subject matter as applied in prior rejection of claim 15 on which this claim depends.
Dreesen et al. further teach, further comprising: generating the flag data with a first bit being a bit one, wherein the first bit corresponds to the index number (see Fig. 1-14, paragraph 0023-0024, 0029-0039, 0043-0054).
Regarding claim 19, Dreesen et al. teach all claimed subject matter as applied in prior rejection of claim 15 on which this claim depends.
Dreesen et al. further teach, wherein the decoding comprises: inverting a first CIM result of the plurality of CIM results according to a first bit of the flag data being a bit one to generate a first decoded CIM result of the plurality of decoded CIM results (see Fig. 1-14, paragraph 0023-0024, 0029-0039, 0043-0055, 0060-0061).
Regarding claim 20, Dreesen et al. teach all claimed subject matter as applied in prior rejection of claim 15 on which this claim depends.
Dreesen et al. further teach, wherein each of the plurality of decoded CIM results corresponds to a column of the memory array, wherein the accumulating comprises: performing a shift-and-add operation to each of the plurality of decoded CIM results according to a place of the column to generate the final result (see Fig. 1-14, paragraph 0023-0024, 0029-0039, 0043-0055, 0060-0062, 0090-0101).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824